- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385412 > HX6228AQFT (Honeywell International Inc.) ER 6C 3#12 3#0 PIN RECP PDF資料下載
參數(shù)資料
| 型號(hào)： | HX6228AQFT |
| 廠商： | Honeywell International Inc. |
| 英文描述： | ER 6C 3#12 3#0 PIN RECP |
| 中文描述： | 128K的× 8靜態(tài)RAM的絕緣硅HX6228 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 153K |
| 代理商： | HX6228AQFT |
HX6228
2
FUNCTIONAL DIAGRAM
CE
NCS
NWE
NOE
MODE
DQ
H
L
H
L
Read
Data Out
H
L
L
X
Write
Data In
X
H
XX
XX
Deselected
High Z
L
X
XX
XX
Disabled
High Z
TRUTH TABLE
SIGNAL DEFINITIONS
A: 0-16
Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Not chip select, when at a low level allows normal operation. When at a high level NCS forces the SRAM to
a precharge condition, holds the data output drivers in a high impedance state and disables all the input
buffers except CE. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
Notes:
X: VI=VIH or VIL
XX: VSS
≤
VI
≤
VDD
NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
NCS
A:3-7,12,14-16
CE
NWE
NOE
WE CS CE
NWE CS CE OE
(0 = high Z)
Column Decoder
Data Input/Output
Row
Decoder
131,072 x 8
Memory
Array
A:0-2, 8-11, 13
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
1 = enabled
Signal
8
DQ:0-7
8
8
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HX6228AQRC | ER 13C 13#16 SKT RECP WALL |
| HX6228AQRT | ER 5C 3#12 2#8 PIN RECP |
| HX6228ASFC | 128K x 8 STATIC RAM-SOI HX6228 |
| HX6228ASFT | 128K x 8 STATIC RAM-SOI HX6228 |
| HX6228ASHC | ER 2C 2#8 PIN RECP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HX6228AQHC | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:128K x 8 STATIC RAM-SOI HX6228 |
| HX6228AQHT | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:128K x 8 STATIC RAM-SOI HX6228 |
| HX6228AQNC | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:128K x 8 STATIC RAM-SOI HX6228 |
| HX6228AQNT | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:128K x 8 STATIC RAM-SOI HX6228 |
| HX6228AQRC | 制造商:HONEYWELL 制造商全稱:Honeywell Solid State Electronics Center 功能描述:128K x 8 STATIC RAM-SOI HX6228 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。