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參數(shù)資料
| 型號： | DP8238 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 137K |
| 代理商： | DP8238 |
Functional Pin Definitions
(Continued)
tion between the CPU, memory, and input/output devices
for instructions and data transfers. A status word (which de-
scribes the current machine cycle) is also outputted on this
data bus during the first microcycle of each machine cycle
(SYNC
e
logic 1).
System Data (DB
7
–DB
0
) Bus:
This bus comprises eight
TRI-STATE input/output lines that connect to the memory
and input/output components of the system. The internal
bidirectional bus driver isolates the DB
7
–DB
0
Data Bus from
the D
7
–D
0
Data Bus.
Status Word Chart
Machine Cycle
Status
Word
Data Bus Bit
Control
Signal
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Instruction Fetch
Memory Read
Memory Write
Stack Read
Stack Write
Input Read
Output Write
Interrupt Acknowledge
Halt Acknowledge
Interrupt Acknowledge While Halt
1
2
3
4
5
6
7
8
9
10
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
1
0
1
MEMR
MEMR
MEMW
MEMR
MEMW
I/OR
I/OW
INTA
(none)
INTA
Block and Connection Diagrams
TL/F/6825–6
Dual-In-Line Package
TL/F/6825–7
Order Number DP8228J, DP8228MJ,
DP8228N, DP8238J, DP8238MJ or
DP8238N
See NS Package Number J28A or N28B
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DP8238M | |
| DP8300 | Single 8-bit Bus Transceiver |
| DP8303A | Single 8-Bit Inverting Bus Transceiver |
| DP8303AJ | Single 8-Bit Inverting Bus Transceiver |
| DP8303J | Single 8-Bit Inverting Bus Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP8238J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller and Bus Driver |
| DP8238J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
| DP8238M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DP8238MJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller and Bus Driver |
| DP8238MJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
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