參數(shù)資料
型號: DG441
廠商: Maxim Integrated Products, Inc.
英文描述: Improved, Quad, SPST Analog Switches(接通電阻85Ω,漏電流0.50nA,導通速率250ns,改進型,四通道單刀單擲模擬開關(guān))
中文描述: 改進的四路、SPST模擬開關(guān)
文件頁數(shù): 7/8頁
文件大小: 127K
代理商: DG441
D
Improved, Quad, S PS T Analog S witc hes
_______________________________________________________________________________________
7
tOFF
0.8 x VOUT
VOUT
0.8 x VOUT
t
f
< 20ns
t
r
< 20ns
50%
0V
0V
+3V
SWITCH
OUTPUT
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
tON
SWITCH
INPUT
LOGIC
INPUT
+3V
IN
D
+15V
V+
V-
-15V
RL
35pF
VOUT
S
CL (INCLUDES FIXTURE AND STRAY CAPACITANCE)
( )
GND
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
VOUT = VD
L
R
LOGIC
INPUT
V
D
DG441
DG442
VOUT
OFF
ON
OFF
VOUT
IN
IN
OFF
OFF
ON
Q=
VOUT
×
CL
-15V
VIN = +3V
V-
V+
IN
GND
S
+15V
RGEN
VGEN
CL
1nF
VOUT
D
DG441
DG442
DG441
DG442
Figure 2. Switching Time
Figure 3. Charge Injection
NETWORK
ANALYZER
SIGNAL
GENERATOR
RGEN = 50
S
D
GND
RL
10dBm
10nF
V+
+15V
IN
0.8V or 2.4V
V-
-15V
10nF
DG441
DG442
NETWORK
ANALYZER
SIGNAL
GENERATOR
RGEN = 50
0.8V or 2.4V
S
IN1
D
GND
RL
10dBm
10nF
V+
+15V
D
IN2
S
0.8V or 2.4V
50
V-
-15V
10nF
DG441
DG442
Figure 4. Off-Isolation Rejection Ratio
Figure 5. Crosstalk (repeat for channels 3 and 4)
______________________________________________T iming Diagrams/Test Circ uits
相關(guān)PDF資料
PDF描述
DG445BDJ Improved Quad SPST CMOS Analog Switches
DG445B Improved Quad SPST CMOS Analog Switches
DG445BDN Improved Quad SPST CMOS Analog Switches
DG445BDY Improved Quad SPST CMOS Analog Switches
DG445 Quad SPST CMOS Analog Switches(功率損耗22nW,快速轉(zhuǎn)換時間120ns的四單刀單擲CMOS模擬開關(guān))
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