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參數(shù)資料
| 型號(hào)： | DG429 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Differential 4-Channel Latchable Analog Multiplexer(帶片上地址和控制鎖存器的雙4通道模擬多路轉(zhuǎn)換器) |
| 中文描述： | 差分4通道鎖存模擬多路復(fù)用器（帶片上地址和控制鎖存器的雙4通道模擬多路轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 102K |
| 代理商： | DG429 |
DG428/429
Vishay Siliconix
Document Number: 70063
S-52433
—
Rev. J, 06-Sep-99
www.vishay.com
11
The internal structure of the DG428/DG429 includes a 5-V
logic interface with input protection circuitry followed by a
latch, level shifter, decoder and finally the switch constructed
with parallel n- and p-channel MOSFETs (see Figure 1).
The input protection on the logic lines A
0
, A
1
, A
2
, EN and
control lines WR, RS shown in Figure 1 minimizes
susceptibility to ESD that may be encountered during handling
and operational transients.
The logic interface is a CMOS logic input with its supply
voltage from an internal +5 V reference voltage. The output of
the input inverter feeds the data input of a D type latch. The
level sensitive D latch continuously places the D
X
input signal
on the Q
X
output when the WR input is low, resulting in
transparent latch operation. As soon as WR returns high the
latch holds the data last present on the D
n
input, subject to the
“
Minimum Input Timing Requirements
”
table.
Following the latches the Q
n
signals are level shifted and
decoded to provide proper drive levels for the CMOS switches.
This level shifting ensures full on/off switch operation for any
analog signal level between the V+ and V
–
supply rails.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard wired to the logic supply or to V+ if
one of the channels will always be used (except during a reset)
or it can be tied to address decoding circuitry for memory
mapped operation. The RS pin is used as a master reset. All
latches are cleared regardless of the state of any other latch
or control line. The WR pin is used to transfer the state of the
address control lines to their latches, except during a reset or
when EN is low (see Truth Tables).
Bus Interfacing
The DG428/DG429 minimize the amount of interface
hardware between a microprocessor system bus and the
analog system being controlled or measured. The internal TTL
compatible latches give these multiplexers write-only memory,
that is, they can be programmed to stay in a particular switch
state (e.g., switch 1 on) until the microprocessor determines
it is necessary to turn different switches on or turn all switches
off (see Figure 10).
The input latches become transparent when WR is held low;
therefore, these multiplexers operate by direct command of
the coded switch state on A
2
, A
1
, A
0
. In this mode the DG428
is identical to the popular DG408. The same is true of the
DG429 versus the popular DG409.
During system power-up, RS would be low, maintaining all
eight switches in the off state. After RS returned high the
DG428 maintains all switches in the off state.
When the system program performs a write operation to the
address assigned to the DG428, the address decoder
provides a CS active low signal which is gated with the WRITE
(WR) control signal. At this time the data on the DATA BUS
(that will determine which switch to close) is stabilizing. When
the WR signal returns to the high state, (positive edge) the
input latches of the DG428 save the data from the DATA BUS.
The coded information in the A
0
, A
1
, A
2
and EN latches is
decoded and the appropriate switch is turned on.
The EN latch allows all switches to be turned off under program
control. This becomes useful when two or more DG428s are
cascaded to build 16-line and larger multiplexers.
Data Bus
RESET
Address
Decoder
ABus
+5 V
V+
V
–
D
+15 V
–
15 V
DG428
Processor
SyBus
15 V
Analog
Inputs
Analog
Output
WR
RS
S
1
S
8
A
0
, A
1
, A
2
, EN
WRITE
FIGURE 10.
Bus Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DG441BDJ | Improved Quad SPST CMOS Analog Switches |
| DG442BDJ | Improved Quad SPST CMOS Analog Switches |
| DG441B | Improved Quad SPST CMOS Analog Switches |
| DG441BDN | Improved Quad SPST CMOS Analog Switches |
| DG441BDY | Improved Quad SPST CMOS Analog Switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DG429A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:2 CHANNEL DRIVERS WITH SPST AND DPST FET SWITCHES |
| DG429AK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Channel Analog Multiplexer |
| DG429AK/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Channel Analog Multiplexer |
| DG429DJ | 功能描述:多路器開關(guān) IC Diff 4:1 Latch Multiplexer/MUX RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| DG429DJ-E3 | 功能描述:多路器開關(guān) IC Diff 4:1 Latch Multiplexer/MUX RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
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