參數(shù)資料
型號： DC956A
廠商： Linear Technology
文件頁數(shù)： 16/40頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2485
軟件下載： QuikEval System
設(shè)計資源： DC956A Design File
DC956A Schematic
標準包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 6.8
數(shù)據(jù)接口： I²C，串行
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2485
已供物品： 板
相關(guān)產(chǎn)品： LTC2485CDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN
LTC2485IDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN
LTC2485IDD#PBF-ND - IC ADC 24BIT I2C 10-DFN
LTC2485CDD#PBF-ND - IC ADC 24BIT I2C 10-DFN
LTC2485
23
2485fc
APPLICATIONS INFORMATION
voltage). Table 6 summarizes the effects of mismatched
source impedance and differences in reference/input
common mode voltages.
Table 6. Suggested Input Conguration for LTC2485
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
Constant
VIN(CM) – VREF(CM)
CEXT > 1nF at Both
IN+ and IN–. Can
Take Large Source
Resistance with
Negligible Error
CEXT > 1nF at Both IN+ and
IN–. Can Take Large Source
Resistance. Unbalanced
Resistance Results in an Offset
Which Can be Calibrated
Varying
VIN(CM) – VREF(CM)
CEXT > 1nF at Both
IN+ and IN–. Can
Take Large Source
Resistance with
Negligible Error
Minimize IN+ and IN–
Capacitors and Avoid Large
Source Impedance
(< 5k Recommended)
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specication can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
will be insignicant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufcient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1μV typical and 10μV maximum offset voltage.
Figure 13. An RC Network at IN+ and IN–
Figure 14. +FS Error vs RSOURCE at IN+ and IN–
Figure 15. –FS Error vs RSOURCE at IN+ and IN–
CEXT
2485 F13
VINCM + 0.5VIN
RSOURCE
IN+
LTC2485
CPAR
20pF
CEXT
VINCM – 0.5VIN
RSOURCE
IN–
CPAR
20pF
RSOURCE (Ω)
1
+FS
ERROR
(ppm)
–20
0
20
1k
100k
2485 F14
–40
–60
–80
10
100
10k
40
60
80
VCC = 5V
VREF = 5V
VIN
+ = 3.75V
VIN
– = 1.25V
TA = 25°C
CEXT = 0pF
CEXT = 100pF
CEXT = 1nF, 0.1μF, 1μF
RSOURCE (Ω)
1
–FS
ERROR
(ppm)
–20
0
20
1k
100k
2485 F15
–40
–60
–80
10
100
10k
40
60
80
VCC = 5V
VREF = 5V
VIN
+ = 1.25V
VIN
– = 3.75V
TA = 25°C
CEXT = 0pF
CEXT = 100pF
CEXT = 1nF, 0.1μF, 1μF
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