WAFER TEST LIMITS (@ V DD = +5.0 V
參數(shù)資料
型號(hào)： DAC8512EPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT SRL LP 5V 8DIP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 16µs
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 2.5mW
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 8-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 8-PDIP
包裝： 管件
輸出數(shù)目和類型： 1 電壓，單極；1 電壓，雙極
采樣率（每秒）： 62.5k
REV. A
–3–
DAC8512
WAFER TEST LIMITS (@ V
DD = +5.0 V
5%, TA = +25 C, applies to part number DAC8512GBC only, unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Relative Accuracy
INL
–2
±3/4
+2
LSB
Differential Nonlinearity
DNL
No Missing Codes
–1
±0.7
+1
LSB
Zero-Scale Error
VZSE
Data = 000H
+1/2
+3
LSB
Full-Scale Voltage
VFS
Data = FFFH
4.085
4.095
4.105
V
LOGIC INPUTS
Logic Input Low Voltage
VIL
0.8
V
Logic Input High Voltage
VIH
2.4
V
Input Leakage Current
IIL
10
A
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VIH = 2.4 V, VIL= 0.8 V, No Load
1.5
2.5
mA
VDD = 5 V, VIL = 0 V, No Load
0.5
1
mA
Power Dissipation
PDISS
VIH = 2.4 V, VIL = 0.8 V, No Load
7.5
12.5
mW
VDD = 5 V, VIL = 0 V, No Load
2.5
5
mW
Power Supply Sensitivity
PSS
V
DD =
±5%
0.002
0.004
%/%
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +10 V
Logic Inputs to GND . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . (TJ max – TA)/
θ
JA
Thermal Resistance
θ
JA
8-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 103
°C/W
8-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 158
°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . +150
°C
Operating Temperature Range . . . . . . . . . . . . . –40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300
°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability .
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8512 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
INL
Temperature
Package
Model
(LSB) Range
Description
Option
DAC8512EP
±1
–40
°C to +85°C 8-Pin P-DIP N-8
DAC8512FP
±2
–40
°C to +85°C 8-Pin P-DIP N-8
DAC8512FS
±2
–40
°C to +85°C 8-Lead SOIC SO-8
DAC8512GBC
±2
+25
°C
Dice
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