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參數(shù)資料
型號(hào)： DAC8143FSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 6/12頁
文件大?。?/td> 0K
描述： IC DAC 12BIT DAISYCHAIN 16SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 380ns
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 500µW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 2.63M
ELECTRICAL CHARACTERISTICS
DAC8143
Parameter
Symbol
Conditions
Min
Typ
Max
Units
STB to SRO Propagation Delay
13
tPD
TA = +25°C
220
ns
TA = Full Temperature Range
300
ns
SRI Data Pulsewidth
tSRI
100
ns
STB1 Pulsewidth (STB1 = 80 ns)
14
tSTB1
80
ns
STB2 Pulsewidth (STB2 = 100 ns)
14
tSTB2
80
ns
STB3 Pulsewidth (STB3 = 80 ns)
14
tSTB3
80
ns
STB4 Pulsewidth (STB4 = 80 ns)
14
tSTB4
80
ns
Load Pulsewidth
tLD1, tLD2
TA = +25°C
140
ns
TA = Full Temperature Range
180
ns
LSB Strobe into Input Register
to Load DAC Register Time
tASB
0ns
CLR Pulsewidth
tCLR
80
ns
POWER SUPPLY
Supply Voltage
VDD
4.75
5
5.25
V
Supply Current
IDD
All Digital Inputs = VIH or VIL
2mA
All Digital Inputs = 0 V or VDD
0.1
mA
Power Dissipation
PD
Digital Inputs = 0 V or VDD
0.5
mW
5 V
× 0.1 mA
Digital Inputs = VIH or VIL
10
mW
5 V
× 2 mA
NOTES
11All grades are monotonic to 12 bits over temperature.
12Using internal feedback resistor.
13Guaranteed by design and not tested.
14Applies to I
OUT1; all digital inputs = VIL, VREF = +10 V; specification also applies for IOUT2 when all digital inputs = VIH.
15V
REF = +10 V, all digital inputs = 0 V.
16Calculated from worst case R
REF: IZSE (in LSBs) = (RREF × ILKG × 4096) /VREF.
17Absolute temperature coefficient is less than +300 ppm/
°C.
18I
OUT, Load = 100 . CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB: tS = propagation delay (tPD) +9 τ, where τ equals measured
time constant of the final RC decay.
19All digital inputs = 0 V.
10V
REF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.
11Calculations from en = √4K TRB where:
K = Boltzmann constant, J/KR = resistance
T = resistor temperature, K B = bandwidth, Hz
12Digital inputs are CMOS gates; I
IN typically 1 nA at +25°C.
13Measured from active strobe edge (STB) to new data output at SRO; C
L = 50 pF.
14Minimum low time pulsewidth for STB
1, STB2, and STB4, and minimum high time pulsewidth for STB 3.
Specifications subject to change without notice.
(@ VDD = +5 V; VREF = +10 V; VOUT1 = V0UT2 = VAGND = VDGND = 0 V; TA = Full
Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)
DAC8143
–3–
REV. C
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