參數(shù)資料
型號(hào)： DAC7654YTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PQFP64
封裝： GREEN, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 15/33頁(yè)
文件大小： 804K
代理商： DAC7654YTG4
DAC7654
SBAS263A NOVEMBER 2003 REVISED DECEMBER 2005
www.ti.com
22
ANALOG OUTPUTS
When VSS = –5V (dual-supply operation), the output
amplifier can swing to within 2.25V of the supply rails over
a range of –40
°C to +85°C. When VSS = 0V (single-supply
operation), and with RLOAD also connected to ground, the
output can swing to within 5mV of ground. Care must be
taken when measuring the zero-scale error when
VSS = 0V. Since the output voltage cannot swing below
ground, the output voltage may not change for the first few
digital input codes (0000h, 0001h, 0002h, etc.) if the output
amplifier has a negative offset.
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance are
very important. A 16-bit converter with a 2.5V full-scale
range has a 1LSB value of 38
V. With a load current of
1mA, series wiring and connector resistance of only 40m
(RW2) will cause a voltage drop of 40V, as shown in
Figure 56. To understand what this means in terms of
system layout, the resistivity of a typical 1-ounce
copper-clad printed circuit board is 1/2 m
per square. For
a 1mA load, a 0.01-inch-wide printed circuit conductor 0.6
inches long will result in a voltage drop of 30
V.
The
DAC7654
offers
a
force
and
sense
output
configuration for the high open-loop gain output amplifier.
This feature allows the loop around the output amplifier to
be closed at the load (as shown in Figure 56), thus
ensuring an accurate output voltage.
DIGITAL INTERFACE
Table 1 shows the basic control logic for the DAC7654.
The interface consists of a signal data clock (CLK) input,
serial data in (SDI), DAC input register load control signal
(LOAD), and DAC register load control signal (LDAC). In
addition, a chip select (CS) input is available to enable
serial communication when there are multiple serial
devices. An asynchronous reset (RST) input, by the rising
edge, is provided to simplify startup conditions, periodic
resets, or emergency resets to a known state, depending
on the status of the reset select (RSTSEL) signal.
V
OUTASense1
V
OUTA
AGND
V
OUTBSense1
V
OUTB
6
5
8
59
58
DAC7654
R
W1
R
W2
V
OUT
R
W1
R
W2
V
OUT
Figure 56. Analog Output Closed-Loop Configuration (1/2 DAC7654). RW represents wiring resistances.
Table 1. DAC7654 Logic Truth Table
A1
A0
CS
RST
RSTSEL
LDAC
LOAD
INPUT REGISTER
DAC REGISTER
MODE
DAC
L
H
X
L
Write
Hold
Write input
A
L
H
L
H
X
L
Write
Hold
Write input
B
H
L
H
X
L
Write
Hold
Write input
C
H
L
H
X
L
Write
Hold
Write input
D
X
H
X
↑
H
Hold
Write
Update
All
X
H
X
H
Hold
All
X
↑
L
X
Reset to zero
All
X
↑
H
X
Reset to mid-scale
All
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