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參數(shù)資料
| 型號： | CYK512K16SCCAU |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 174K |
| 代理商： | CYK512K16SCCAU |
ADVANCE
INFORMATION
CYK512K16SCCAU
MoBL3
Document #: 38-05425 Rev. **
Page 5 of 10
t
SK
Write Cycle
[14]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Address Skew
10
ns
Write Cycle Time
CE LOW and CE
2
HIGH
to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[12, 13]
WE HIGH to Low-Z
[12, 13]
70
60
60
0
0
45
60
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
5
Switching Characteristics
Over the Operating Range (continued)
[11]
Parameter
Description
70 ns
Unit
Min.
Max.
Switching Waveforms
Notes:
14.Internal memory write time is defined by overlap of WE, CE
= V
, BHE and/or BLE = V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to edge of signal that terminates the write.
15.WE is HIGH for read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
Read Cycle 1 (Address Transition Controlled)
[15]
tSK
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PDF描述 |
|---|---|
| CYL2T0201-AIP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CYM1910PV-25C | SYNC SRAM|16KX68|CMOS|DIP|104PIN|PLASTIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK512K16SCCAU-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8-Mbit (512K x 16) Pseudo Static RAM |
| CYK512K16SCCAU-55BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 8MBIT 512KX16 55NS 48FBGA - Tape and Reel |
| CYK512K16SCCAU-70BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8-Mbit (512K x 16) Pseudo Static RAM |
| CYL | 制造商:EDI 制造商全稱:Electronic devices inc. 功能描述:HIGH VOLTAGE CYLINDER SILICON RECTIFIERS |
| CYL2T0201-AIP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Framers and Mappers |
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