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參數(shù)資料
| 型號： | CY7C1305BV25-100BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| 中文描述： | 1M X 18 QDR SRAM, 3 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大小： | 247K |
| 代理商： | CY7C1305BV25-100BZC |
PRELIMINARY
18-Mbit Burst of 4 Pipelined SRAM with
QDR Architecture
CY7C1305BV25
CY7C1307BV25
Cypress Semiconductor Corporation
Document #: 38-05630 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised July 29, 2004
Features
Separate independent Read and Write data ports
Supports concurrent transactions
167-MHz clock for high bandwidth
2.5 ns Clock-to-Valid access time
4-Word Burst for reducing the address bus frequency
Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two output clocks (C and C) accounts for clock skew
and flight time mismatching
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–1.9V)
JTAG interface
Configurations
CY7C1305BV25 – 1M x 18
CY7C1307BV25 – 512K x 36
Functional Description
The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305BV25) and four
36-bit words (CY7C1307BV25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1307BV25 | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| CY7C1307BV25-100BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| CY7C1307BV25-133BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| CY7C1307BV25-167BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| CY7C1305BV25-133BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1305BV25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mx18 2.5V QDR 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1305BV25-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mx18 2.5V QDR 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1305TC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1305TV25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 NV靜態(tài)隨機(jī)存取存儲器 167 MHz 2.5V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1305TV25-167BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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