- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379059 > CY7C1250V18-300BZXC (CYPRESS SEMICONDUCTOR CORP) 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1250V18-300BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 1M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 1037K |
| 代理商： | CY7C1250V18-300BZXC |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
36-Mbit DDR-II+ SRAM 2-Word
Burst Architecture (2.0 Cycle Read Latency)
CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Cypress Semiconductor Corporation
Document Number: 001-06348 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 15, 2007
Features
36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
300 MHz to 375 MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) @ 375 MHz
Read latency of 2.0 clock cycles
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high
speed systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
Core V
DD
= 1.8V ± 0.1V; IO V
DDQ
= 1.4V to V
DD[1]
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both in Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1246V18 – 4M x 8
CY7C1257V18 – 4M x 9
CY7C1248V18 – 2M x 18
CY7C1250V18 – 1M x 36
Functional Description
The CY7C1246V18, CY7C1257V18, CY7C1248V18, and
CY7C1250V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of
an SRAM core with advanced synchronous peripheral
circuitry. Addresses for read and write are latched on alternate
rising edges of the input (K) clock. Write data is registered on
the rising edges of both K and K. Read data is driven on the
rising edges of both K and K. Each address location is
associated with two 8-bit words (CY7C1246V18), 9-bit words
(CY7C1257V18), 18-bit words (CY7C1248V18), or 36-bit
words (CY7C1250V18) that burst sequentially into or out of the
device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, which share the
same physical pins with the data inputs, D) are tightly matched
to the two output echo clocks CQ/CQ, eliminating the need to
capture data separately from individual DDR SRAMs in the
system design.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
375 MHz
375
1210
333 MHz
333
1080
300 MHz
300
1000
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
V
DDQ
= 1.4V to V
DD
.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1304V25 | 9-Mb Pipelined SRAM with QDR Architecture(帶QDR結(jié)構(gòu)的9-M位流水線式 SRAM) |
| CY7C1305BV25-100BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| CY7C1307BV25 | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| CY7C1307BV25-100BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
| CY7C1307BV25-133BZC | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1250V18-333BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36M Q2+ B2 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1250V18-333BZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1250V18-333BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36-Mbit DDR-II+ 靜態(tài)隨機(jī)存取存儲(chǔ)器 1.8volts RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1250XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1262XV18-366BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (2Mx18) 1.8v 366MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。