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參數(shù)資料
| 型號： | CY7B991V-7JCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Programmable Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 293K |
| 代理商： | CY7B991V-7JCT |
CY7B991V
3.3V RoboClock
Document Number: 38-07141 Rev. *C
Page 7 of 14
Figure 7
shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output enables the system designer to clock different
subsystems on opposite edges without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase,
but still is aligned within the skew specification.
The divided outputs offer a zero delay divider for portions of the
system that divide the clock by either two or four, and still remain
within a narrow skew of the “1X” clock. Without this feature, an
external divider is added, and the propagation delay of the
divider adds to the skew between the different clock signals.
These divided outputs, coupled with the Phase Locked Loop,
enable the LVPSCB to multiply the clock rate at the REF input by
either two or four. This mode allows the designer to distribute a
low frequency clock between various portions of the system. It
also locally multiplies the clock rate to a more suitable frequency,
while still maintaining the low skew characteristics of the clock
driver. The LVPSCB performs all of the functions described in
this section at the same time. It can multiply by two and four or
divide by two (and four) at the same time that it shifts its outputs
over a wide range or maintains zero skew between selected
outputs.
.
Figure 7. Multi-Function Clock Driver
20 MHz
DISTRIBUTION
CLOCK
80 MHz
INVERTED
Z
0
20 MHz
80 MHz
ZERO SKEW
80 MHz
SKEWED –3.125 ns (–4t
U
)
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
LOAD
LOAD
LOAD
LOAD
Z
0
Z
0
Z
0
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PDF描述 |
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| CY7B991V-7JXC | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-7JXCT | Low Voltage Programmable Skew Clock Buffer |
| CY7C006V | 3.3V 16K x 8 Dual-Port Static RAM(3.3V 16Kx 8 位雙端口靜態(tài)RAM) |
| CY7C1016V | 3.3V 16Kx9 Dual-Port Static RAM(3.3V 16Kx 9 位雙端口靜態(tài)RAM) |
| CY7C138V | 3.3V 4Kx 8 Dual-Port Static RAM(3.3V 4Kx 8 位雙端口靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B991V-7JXC | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-7JXCT | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B992 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B992.2JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B992.2JCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
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