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參數(shù)資料
| 型號(hào)： | CY7B991V-7JCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Low Voltage Programmable Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 293K |
| 代理商： | CY7B991V-7JCT |
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CY7B991V
3.3V RoboClock
Document Number: 38-07141 Rev. *C
Page 3 of 14
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input. They generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency that is used by the time unit generator
to create discrete time units, selected in the skew select matrix.
The operational range of the VCO is determined by the FS
control pin. The time unit (t
U
) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1
.
Skew Select Matrix
The skew select matrix is comprised of four independent
sections. Each section has two low skew, high fanout drivers
(xQ0, xQ1), and two corresponding three level function select
(xF0, xF1) inputs.
Table 2
shows the nine possible output
functions for each section as determined by the function select
inputs. All times are measured with respect to the REF input
assuming that the output connected to the FB input has 0t
U
selected.
Table 1. Frequency Range Select and t
U
Calculation
[
1
]
f
NOM
(MHz)
t
U
=
FS
[2, 3]
where N =
44
26
16
Approximate
Frequency (MHz) At
Which t
U
= 1.0 ns
Min
Max
LOW
MID
HIGH
15
25
40
30
50
80
22.7
38.5
62.5
NOM
N
×
f
Table 2. Programmable Skew Configurations
[1]
Function Selects
1F1, 2F1,
3F1, 4F1
3F0, 4F0
2Q0, 2Q1
LOW
LOW
LOW
MID
LOW
HIGH
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Functions
1Q0, 1Q1,
3Q0, 3Q1
1F0, 2F0,
4Q0, 4Q1
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
Divide by 2 Divide by 2
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Divide by 4
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Inverted
Notes
1. For all three state inputs, HIGH indicates a connection to V
CC
, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to V
/2.
2. The level to be set on FS is determined by the “normal” operating frequency (f
) of the V
CO
and Time Unit Generator (see ). Nominal frequency (f
) always
appears at 1Q0 and the other outputs when they are operated in their undivided modes (see
Table 2
). The frequency appearing at the REF and FB inputs is f
when the output connected to FB is undivided. The frequency of the REF and FB inputs is f
NOM
/2 or f
NOM
/4 when the part is configured for a frequency multiplication
using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until V
CC
has reached 2.8V.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B991V-7JXC | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-7JXCT | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B992 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B992.2JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B992.2JCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
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