參數(shù)資料
型號: CY7B991V-7JCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: Low Voltage Programmable Skew Clock Buffer
中文描述: 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
封裝: PLASTIC, LCC-32
文件頁數(shù): 12/14頁
文件大?。?/td> 293K
代理商: CY7B991V-7JCT
CY7B991V
3.3V RoboClock
Document Number: 38-07141 Rev. *C
Page 12 of 14
Switching Characteristics
7 Option
Over the Operating Range
[2, 10]
Parameter
Description
CY7B991V–7
Typ
Unit
Min
15
25
40
5.0
5.0
Max
30
50
80
f
NOM
Operating Clock
Frequency in MHz
FS = LOW
[1, 2]
FS = MID
[1, 2]
FS = HIGH
[1, 2]
MHz
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
t
SKEW2
t
SKEW3
t
SKEW4
t
DEV
t
PD
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched Pair Skew (XQ0, XQ1)
[14, 15]
Zero Output Skew (All Outputs)
[14, 16]
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
[13, 17]
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
[14, 18]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
[14, 18]
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
[14, 18]
Device-to-Device Skew
[13, 19]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
[19]
Output HIGH Time Deviation from 50%
[20]
Output LOW Time Deviation from 50%
[20]
Output Rise Time
[20, 21]
Output Fall Time
[20, 21]
PLL Lock Time
[22]
Cycle-to-Cycle Output
Jitter
ns
ns
See
Table 1
0.1
0.3
0.6
1.0
0.7
1.2
0.25
0.75
1.0
1.5
1.2
1.7
1.65
+0.7
+1.2
3
3.5
2.5
2.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
–0.7
–1.2
0.0
0.0
0.15
0.15
1.5
1.5
RMS
[12]
Peak-to-Peak
[12]
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CY7B991V-7JXC 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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