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參數(shù)資料
| 型號： | CY28323OXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BROOKDALE GPENT4 48SSOP |
| 標準包裝： | 30 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 248MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 48-SSOP |
| 包裝： | 管件 |
CY28323PVC
... Document #: 38-07004 Rev. *B Page Page 5 of 21 of 21
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or
disabled.
The register associated with the Serial Data Interface
initializes to its default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol.
The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block read or block write operation
1 = Byte read or byte write operation
6:0
Byte offset for byte read or byte write operation. For block read or block write operations, these
bits should be ‘0000000’.
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29:36
Data byte 0 – 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 – 8 bits
30:37
Byte count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
...
Data Byte N/Slave Acknowledge...
39:46
Data byte from slave – 8 bits
...
Data Byte N – 8 bits
47
Acknowledge
...
Acknowledge from slave
48:55
Data byte from slave – 8 bits
...
Stop
56
Acknowledge
...
Data bytes from slave/Acknowledge
...
Data byte N from slave – 8 bits
...
Not Acknowledge
...
Stop
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28323OXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Brookdale RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28323PVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28324 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel Pentium 4 CPU and Chipsets |
| CY28324_02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
| CY28324PVC | 制造商:Cypress Semiconductor 功能描述:PLL Frequency Generator Dual 48-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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