參數(shù)資料
型號： CXP83621
廠商： Sony Corporation
英文描述： CMOS 8-bit Single Chip Microcomputer
中文描述： 的CMOS 8位單片機
文件頁數(shù)： 23/30頁
文件大?。?/td> 423K
代理商： CXP83621
– 23 –
CXP83620/83624, CXP83621/83625
Serial Transfer (CH1)
(Ta = –20 to +75°C, V
DD
= 4.5 to 5.5V, Vss = 0V)
Item
SCK cycle time
t
KCY
SCK1
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
1000
8000/fc
400
4000/fc – 50
100
200
200
100
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1
SI1
SI1
SO1
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK high and low level
widths
SI input setup time
(for SCK
↑
)
SI input hold time
(for SCK
↑
)
SCK
↓ →
SO delay time
Symbol
Pin
Conditions
Min.
Max.
Unit
Note 1)
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
t
sys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2)
SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3)
The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Note 4)
The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to normal.
Serial Transfer (CH1)
(Ta = –20 to +75°C, V
DD
= 2.7 to 3.3V, Vss = 0V)
Item
SCK cycle time
t
KCY
SCK1
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
1000
8000/fc
400
4000/fc – 100
100
200
200
100
250
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1
SI1
SI1
SO1
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK high and low level
widths
SI input setup time
(for SCK
↑
)
SI input hold time
(for SCK
↑
)
SCK
↓ →
SO delay time
Symbol
Pin
Conditions
Min.
Max.
Unit
Note 1)
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
t
sys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2)
SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3)
The load condition for the SCK1 output mode, SO1 output delay time is 50pF.
Note 4)
The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to high.
相關PDF資料
PDF描述
CXP83624 Terminal Block,Cable Mount,PLUG,3 Contacts,SKT,DETENT
CXP83625 CMOS 8-bit Single Chip Microcomputer
CXP83625Q Microcontroller
CXP83620Q Microcontroller
CXP83620R Microcontroller
相關代理商/技術參數(shù)
參數(shù)描述
CXP83621Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Microcontroller
CXP83624 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS 8-bit Single Chip Microcomputer
CXP83624Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Microcontroller
CXP83624R 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Microcontroller
CXP83625 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS 8-bit Single Chip Microcomputer
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