參數(shù)資料
型號(hào)： CS8126YDPS7
廠商： ZF Electronics Corporation
英文描述： 5V, 750mA Low Dropout Linear Regulator with Delayed RESET
中文描述： 5V的，七五○毫安低壓降線性穩(wěn)壓器的延遲復(fù)位
文件頁(yè)數(shù)： 2/9頁(yè)
文件大?。?/td> 207K
代理商： CS8126YDPS7
2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics: T
A
= -40C to +125C, T
= -40C to +150C, V
= 6 to 26V, I
O
=5 to 500mA,
R
RESET
= 4.7k to V
CC,
unless otherwise noted.
Absolute Maximum Ratings
Power Dissipation.............................................................................................................................................Internally Limited
Peak Transient Voltage (46V Load Dump) .................................................................................................................-50V, 60V
Output Current.................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model)..............................................................................................................................4kV
Junction Temperature.............................................................................................................................................-40C to 150C
Storage Temperature...............................................................................................................................................-55C to 150C
Lead Temperature Soldering Wave Solder (through hole styles only)..........................................10 sec. max, 260C peak
Reflow (SMD styles only) ..........................................60 sec. max above 183C, 230C peak
I
Output Stage (V
OUT
)
Output Voltage
Dropout Voltage
Supply Current
4.85
5.00
0.35
2
6
55
5
10
75
5.15
0.60
7
12
100
50
50
V
V
I
OUT
= 500mA
I
OUT
2 10mA
I
OUT
2 100mA
I
OUT
2 500mA
V
IN
= 6 to 26V, I
OUT
= 50mA
I
OUT
= 50 to 500mA, V
IN
= 14V
f = 120Hz, V
IN
= 7 to 17V,
I
OUT
= 250mA
mA
Line Regulation
Load Regulation
Ripple Rejection
mV
mV
dB
54
Current Limit
Overvoltage Shutdown
Maximum Line Transient
Reverse Polarity Input
Voltage DC
Reverse Polarity Input
Voltage Transient
Thermal Shutdown
0.75
32
1.20
A
V
V
V
40
V
OUT
2 5.5V
V
OUT
3 -0.6V, 10 Load
95
-30
-15
1% Duty Cycle, T < 100ms,
10 Load
Guaranteed by Design
-80
V
150
180
210
C
I
and Delay Functions
Delay Charge Current
Threshold
RESET
V
Delay
= 2V
V
OUT
Increasing, V
RT(ON)
V
OUT
Decreasing, V
RT(OFF)
V
RH
= V
RT(ON)
- V
RT(OFF)
Charge, V
DC(HI)
Discharge, V
DC(LO)
5
10
4.90
4.70
200
3.50
3.10
400
0.1
0
15
μA
V
V
mV
V
V
mV
V
μA
4.65
4.50
150
3.25
2.85
200
V
OUT
- 0.01
V
OUT
- 0.15
250
3.75
3.35
800
0.4
10
Hysteresis
Delay Threshold
Delay Hysteresis
Output Voltage Low
Output Leakage
Current
Delay Capacitor
Discharge Voltage
Delay Time
1V < V
OUT
< V
RTL
, 3k to V
OUT
V
OUT
> V
RT(ON)
Discharge Latched òONó,
V
OUT
> V
RT
C
Delay
= 0.1μF* (Note 1)
0.2
0.5
V
16
32
48
ms
Delay Time =
= C
Delay
x 3.2 x 10
5
(typ)
Note 1: assumes ideal capacitor
C
Delay
′
V
Delay
Threshold Charge
I
Charge
RESET
RESET
RESET
RESET
C
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