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參數(shù)資料
| 型號： | CS4352-DZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 0K |
| 描述： | IC DAC STER 102DB 192KHZ 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 158mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 192k |
| 配用： | 598-1518-ND - BOARD EVAL FOR CS4352 DAC |
14
DS684F2
CS4352
4.7
Popguard Transient Control
The CS4352 uses a novel technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended, single-supply converters. It is activat-
ed inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing
the appropriate DC-blocking capacitors.
4.7.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.
Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies-
cent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins.
This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-
cent voltage, minimizing audible power-up transients.
4.7.2
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases, and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted that allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready
for the next power-on.
4.7.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.8
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio
is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks
and pops that can occur in any single-ended, single-supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Please see the CDB4352 data sheet for a suggested mute circuit for dual-supply systems. Alternately, the
FET muting circuit from the CS4351 data sheet may be used as well. This FET circuit must be placed in
series after the RC filter; otherwise noise may occur during muting conditions. Further ESD protection will
need to be taken into consideration for the FET used.
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| CS4353-CNZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 3.3V Str DAC w/2Vrms line output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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