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參數(shù)資料
| 型號(hào)： | COP688CL |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit Microcontroller(8位微控制器) |
| 中文描述： | 8位微控制器（8位微控制器） |
| 文件頁數(shù)： | 18/41頁 |
| 文件大?。?/td> | 565K |
| 代理商： | COP688CL |
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Timers
(Continued)
Figure 8 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxAoutput
pin. The underflows can also be programmed to generate
interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control
enable flags, TxENA and TxENB, allow the interrupts from
the timer underflow to be enabled or disabled. Setting the
timer enable flag TxENA will cause an interrupt when a timer
underflow causes the RxA register to be reloaded into the
timer. Setting the timer enable flag TxENB will cause an
interrupt when a timer underflow causes the RxB register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.
Either or both of the timer underflow interrupts may be
enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of
the PWM output. Alternatively, the user may choose to inter-
rupt on both edges of the PWM output.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is clocked by the input signal from the TxApin. The
Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to
be clocked either on a positive or negative edge from the
TxA pin. Underflows from the timer are latched into the
TxPNDA pending flag. Setting the TxENA control flag will
cause an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 9 shows a block diagram of the timer in External
Event Counter mode.
Note:
The PWM output is not available in this mode since the TxApin is being
used as the counter input clock.
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed t
c
rate. The two registers, RxA and RxB, act as capture regis-
DS009766-13
FIGURE 8. Timer in PWM Mode
DS009766-14
FIGURE 9. Timer in External Event Counter Mode
C
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| COP688CL-XXX/N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:General Description |
| COP688CL-XXX/V | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:General Description |
| COP688CS | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory, Comparators and USART |
| COP688CS-XXX/V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|8-BIT|COP800 CPU|CMOS|LDCC|44PIN|PLASTIC |
| COP688EB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based Microcontrollers with 8k Memory, CAN Interface, 8-Bit A/D, and USART |
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