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參數(shù)資料
| 型號： | CLC012AJE |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Adaptive Cable Equalizer for ITU-T G.703 Data Recovery |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 567K |
| 代理商： | CLC012AJE |
Output Interfacing
(Continued)
TERMINATING PHYSICALLY SEPARATED OUTPUTS
When the two outputs must be routed to physically separate
locations, the circuit in Figure 6 may be applied. Alterna-
tively, if load termination is desired, the circuit in Figure 7
may be used. The resistive divider network provides 75
ter-
mination and establishes proper ECL levels. This circuit con-
sumes slightly more power than the previous circuits.
Design Guidelines
SELECTING THE AUTOMATIC EQUALIZER CAPACITOR
The AEC capacitor sets the loop time constant
τ
for the
equalizer’s adaptive loop response time. The following for-
mula is used to set the loop time constant:
τ
= R
C
AEC
10
6
R is a conversion factor that is set by internal equalizer pa-
rameters and cable length. For Belden 8281 coaxial cable,
the R values are (
τ
= μs, C
AEC
in pF):
Cable
Length
100 meters
200 meters
300 meters
R Value
(Ohms)
15000
20000
32000
For example, a C
value of 100 pF results in an adaptive
loop time constant of 2 μs at 200 meters of cable.
CONNECTION AND OPERATION OF LOS AND MUTE
Loss of Signal (LOS)
is a CMOS output that indicates the
presence of equalized data from the filter. This LOS output
can be connected to MUTE to suspend changes in the data
outputs DO and DO, if no valid signal exists. This simple
configuration prevents random output transitions due to
noise. For sparse transition patterns it is recommended that
a capacitor be connected to LOS as shown in Figure 1
Add a capacitor to pin 5 to slow the response time of Loss of
Signal when LOS is connected to MUTE. The capacitor re-
duces sensitivity to pathological patterns. Pathological pat-
terns are defined as sparse data sequences with few transi-
tions.
OUTPUT EYE MONITOR OEM CONNECTIONS
The OEM is a high-speed, buffered output for monitoring the
equalized eye pattern prior to the output comparator. Its out-
put is designed to drive an AC-coupled 50
coaxial cable
with a series 50
backmatch resistor. The cable should be
terminated with 50
at the oscilloscope. Figure 1 shows a
schematic with a typical connection.
MINIMUM DATA TRANSITIONS
The CLC012 specifies a minimum transition rate. For the
CLC012 this sets the minimum data rate for transmitting data
through any cable medium. The CLC012 minimum average
transition density is found in the Electrical Characteristics
section of the datasheet.
POWER SUPPLY OPERATION AND THERMAL
CONSIDERATIONS
The CLC012 operates from either +5V or 5.2V single sup-
plies. Refer to Figure 1 when operating the part from +5V.
When operating with a 5.2V supply, the V
pins should be
bypassed to ground. The evaluation board and associated
literature provide for operation from either supply.
Maximum power dissipation occurs at minimum cable
length. Under that condition, I
CC
= 58 mA.
Total power dissipated:
P
T
= (58 mA)(5V) = 290 mW
Power in the load:
P
L
= (0.7V)(11 mA) + (37.5)(11 mA)
2
= 12 mW
Maximum power dissipated on the die:
P
DMAX
= P
T
–P
L
= 278 mW
Junction Temperature =
(
θ
JA
)(278 mW) + T
A
= T
A
+ 26C
Layout and Measurement
The printed circuit board layout for the CLC012 requires
proper high-speed layout to achieve the performance speci-
fications found in the datasheet. The following list contains a
few rules to follow:
1.
Use a ground plane.
2.
Decouple power pins with 0.1 μF capacitors placed
≤
0.1” (3mm) from the power pins.
3.
Design transmission strip lines from the CLC012’s input
and output pins to the board connectors.
4.
Route outputs away from inputs.
5.
Keep ground plane
≥
0.025” (0.06mm) away from the in-
put and output pads.
Figure 8 shows a block level measurement diagram, while
Figure 15on depicts a detailed schematic.Apseudo-random
pattern generator with low output jitter was used to provide a
NRZI pattern to create the eye diagrams shown in the
Typi-
cal Performance Characteristics
section.
Since most pattern generators have a 50
output imped-
ance, a translation can be accomplished using a CLC005
Cable Driver as an impedance transformer. A wide band-
width oscilloscope is needed to observe the high data rate
eye pattern. When monitoring a single output that is termi-
nated at both the equalizer output and the oscilloscope, the
effective output load is 37.4
. Consequently, the signal
swing is half that observed for a single-ended 75
termination.
DS100145-27
FIGURE 7. Alternative Load Terminated
Output Interface
www.national.com
10
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| CLC014 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Adaptive Cable Equalizer for High-Speed Data Recovery |
| CLC014_03 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Adaptive Cable Equalizer for High-Speed Data Recovery |
| CLC014AJE | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:IC CABLE EQUALIZER HI SPEED SMD 制造商:Texas Instruments 功能描述:IC, ADAPTIVE CABLE EQUALIZER, SOIC-14, IC Function:Adaptive Cable Equalizer, Bri |
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