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參數(shù)資料
| 型號： | CLC011ACQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Serial Digital Video Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | CLC011ACQ |
Input Interfacing—Control Inputs
(Continued)
FE is normally conditioned in one of three ways.
1.
FE tied high.
This is the most common mode for FE. In
this mode, when a TRS is received, PCLK is aligned to
the new TRS. If a new sync position (NSP) is identified,
the NSP output will go high until the next TRS is re-
ceived.
2.
FE tied to NSP.
When in this mode, if a TRS that is out
of phase with the existing PCLK is detected, NSP will go
high, but the phase of PCLK will not be adjusted. If the
next TRS received is in-phase with PCLK, NSP will go
low and the decoder will continue without changing its
state. If the next TRS to arrive is out of phase with PCLK,
then PCLK’s phase is adjusted to meet the new TRS
and NSP is made low. Single erroneous TRS pulses are
ignored in this mode, but if they persist, the decoder will
re-adjust PCLK to properly frame the data.
3.
FE held low during active video.
The automatic fram-
ing feature using the TRS may be disabled in cases
where non-SMPTE 259M signals are being processed.
In some applications like computer-generated anima-
tion, the serial video data may not adhere to the SMPTE
259M standard and patterns that resemble TSR’s can
occur within the active video line. When such patterns
occur and to prevent the CLC011 from attempting re-
framing, make FE a logic low during the active video
line.
Output Interface—Output Logic
Levels
All outputs of the CLC011 are CMOS compatible. They can
be programmed to provide appropriate output logic levels to
connect to following stages operating from supplies of 3.0V
to 5.5V. Output voltages are set by applying the positive sup-
ply voltage powering the following stage to VDP, which con-
trols PD0-9, EAV, TRS and NSP, and VCP, which controls
PCLK. An example of the CLC011, powered from +5V, driv-
ing a device powered from a 3.3V supply is shown in Figure
5
The CLC011’s output drivers, shown simplified in Figure 6
are designed to maintain a constant, controlled slew rate re-
gardless of load. This design results in lower output switch-
ing noise injection via the supply pins and into other circuitry.
Even so, it is recommended that the CLC011 and other digi-
tal circuitry be separated from analog circuitry and cable
equalizers.
DS100086-7
FIGURE 5. Typical Output Interface
DS100086-8
FIGURE 6. Simplified Output Buffer Schematic
www.national.com
6
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC011BCQ | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:SERIAL DIGITAL VIDEO DECODER SMD 制造商:Texas Instruments 功能描述:IC, VIDEO DECODER, 10BIT, LCC-8, Resolution (Bits):10bit, Input Format:Digital, |
| CLC011BCQ/NOPB | 功能描述:IC DECODER VIDEO SER DIG 28-PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| CLC011PCASM | 功能描述:BOARD EVALUATION FOR CLC011 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| CLC012 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Adaptive Cable Equalizer for ITU-T G.703 Data Recovery |
| CLC012_03 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Adaptive Cable Equalizer for ITU-T G.703 Data Recovery |
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