參數(shù)資料
型號: CDB4329
廠商: Cirrus Logic, Inc.
英文描述: 20-Bit, Stereo D/A Converter for Digital Audio
中文描述: 20位,立體聲D / A轉(zhuǎn)換器的數(shù)字音頻
文件頁數(shù): 3/36頁
文件大?。?/td> 1540K
代理商: CDB4329
CS4329
DS153F1
3
ANALOG CHARACTERISTICS (CONTINUED)
Notes: 1.
Triangular PDF Dithered Data
AUTO-MUTE active. See parameter definitions
The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz,
the passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.
Group Delay for Fs=48 kHz 25/48 kHz=520
μ
s
Specified for a fully differential output ±((AOUT+)-(AOUT-)). See Figure 12.
2.
3.
4.
5.
SWITCHING CHARACTERISTICS
(T
A
= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = VA = 5.25
to 4.75 Volts; C
L
= 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Analog Output
Differential Full Scale Output Voltage
Output Common Mode Voltage
Differential Offset
AC Load Resistance
Load Capacitance
(Note 5)
1.90
-
-
4
-
2.0
2.2
3
-
-
2.10
-
15
-
100
Vrms
V
mV
k
pf
R
L
C
L
Parameter
Symbol
Fs
Min
1
10
10
21
21
31
32
Typ
-
-
-
-
-
-
-
Max
50
-
-
-
-
-
-
Unit
kHz
ns
ns
ns
ns
ns
ns
Input Sample Rate
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
External SCLK Mode
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
MCLK / LRCK = 512
MCLK / LRCK = 512
MCLK / LRCK = 384
MCLK / LRCK = 384
MCLK / LRCK = 256
MCLK / LRCK = 256
t
sclkl
t
sclkh
t
sclkw
20
20
-
-
-
-
-
-
ns
ns
ns
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
SCLK Period
t
slrd
t
slrs
t
sdlrs
t
sdh
20
20
20
20
-
-
-
-
-
-
-
-
ns
ns
ns
ns
SCLK / LRCK = 64
t
sclkw
-
-
ns
SDATA valid to SCLK rising setup time
t
sdlrs
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 256 or 512
t
sdh
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384
t
sdh
-
-
ns
128 Fs
)
-------1
64 Fs
)
-------1
512 Fs
)
-------1
10
+
512 Fs
)
-------1
15
+
384 Fs
)
-------1
15
+
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