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參數(shù)資料
| 型號： | CDB4328 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | 18-Bit, Stereo D/A Converter for Digital Audio |
| 中文描述： | 18位，立體聲D / A的數(shù)字音頻轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 831K |
| 代理商： | CDB4328 |
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GENERAL DESCRIPTION
The CS4328 is a complete stereo digital-to-ana-
log system designed for digital audio. The
system accepts data at standard audio frequen-
cies, such as 48 kHz, 44.1 kHz, and 32 kHz; and
produces line-level outputs.
The architecture includes an 8
×
oversampling fil-
ter followed by a 64
×
oversampled one-bit
delta-sigma modulator. The output from the one
bit modulator controls the polarity of a reference
voltage which is then passed through an ultra-
linear analog low-pass filter. The result is
line-level outputs with no need for further filter-
ing.
SYSTEM DESIGN
Very few external components are required to
support the DAC. Normal power supply decou-
pling components and voltage reference bypass
capacitors are all that’s required.
System Clock Input
The master clock (XTI/XTO) input to the DAC
is used to operate the digital interpolation filter
and the delta-sigma modulator. The master clock
can be either a crystal placed across the XTI and
XTO pins, or an external clock input to the XTI
pin with the XTO pin left floating.
The frequency of XTI/XTO is determined by the
desired Input Word Rate, IWR, and the setting of
the Clock Select pin, CKS. IWR is the frequency
at which words for each channel are input to the
DAC and is equal to LRCK frequency. Setting
CKS low selects an XTI/XTO frequency of
256
×
IWR while setting CKS high selects
384
×
IWR. The ACKO pin will always be
128
×
IWR and is used by the analog low-pass
smoothing filter. Table 1 illustrates various audio
word rates and corresponding frequencies used
in the DAC.
The remaining system clocks, LRCK and BICK,
must be synchronously derived from XTI/XTO.
If the CS4328 internal oscillator is used, the cir-
cuit must be configured and XTO buffered as
shown in Figure 1. XTI/XTO can be divided to
produce LRCK and BICK using a synchronous
counter such as 74HC590. Notice that the value
of the capacitor on XTO is 10 pF and the XTI
capacitor is 15 pF, which allows for 5 pF of gate
and stray capacitance.
It is also possible to divide ACKO, 128
×
IWR,
to derive BICK and LRCK. However, external
circuitry must be used to apply a "kick-start"
pulse to LRCK in order to activate ACKO. The
sequence for the cancellation of RESET, begin-
ning of calibration and activation of ACKO is
shown in Figure 2 with the required transitions
indicated by arrows. A momentary loss of
XTI/XTO or power will require a "kick-start"
pulse to resume operation.
Serial Data Interface
Data is input to the CS4328 via three serial input
pins; SDATAI is the serial data input, BICK is
the serial data clock and LRCK defines the chan-
nel and delineation of data. The DAC supports
four serial data formats which are selected via
the digital input format pins DIF0 and DIF1. The
different formats control the relationship of
LRCK to SDATAI and the edge of BICK used to
LRCK
(kHz)
32
32
44.1
44.1
48
48
CKS
XTI/XTO
(MHz)
8.192
12.288
11.2896
16.9344
12.288
18.432
ACKO
(MHz)
4.096
4.096
5.6448
5.6448
6.144
6.144
low
high
low
high
low
high
Table 1. Common Clock Frequencies
CS4328
6
DS62F3
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