參數(shù)資料
型號: CDB43122
廠商: Cirrus Logic, Inc.
英文描述: 122dB, 24-Bit, 192kHz DAC for Digital Audio
中文描述: 122分貝,24位,192kHz的數(shù)字音頻數(shù)模轉(zhuǎn)換器
文件頁數(shù): 9/28頁
文件大?。?/td> 523K
代理商: CDB43122
CS43122
9
SWITCHING CHARACTERISTICS
(T
A
= -10 to 70° C; Logic 0 = AGND = DGND; Logic
1 = VD = 5.25 to 3.0 Volts; C
L
= 20 pF)
Parameter
Symbol
Fs
Fs
Fs
Min
16
45
95
45
Typ
-
-
-
50
Max
55
105
200
55
Unit
kHz
kHz
kHz
%
Input Sample Rate (Operational Mode 0)
(Operational Mode 1)
(Operational Mode 2)
LRCK Duty Cycle
MCLK Frequency
(Operational Mode 0, 256 Fs)
(Operational Mode 1, 128 Fs)
(Operational Mode 2, 64 Fs)
MCLK Frequency
(Operational Mode 0, 384 Fs)
4.096
-
14.08
MHz
(Operational Mode 1, 192 Fs)
(Operational Mode 2, 96 Fs)
MCLK Frequency
(Operational Mode 0, 512 Fs)
6.144
-
21.12
MHz
(Operational Mode 1, 256 Fs)
(Operational Mode 2 , 128 Fs)
MCLK Frequency
(Operational Mode 0, 768 Fs)
8.192
-
28.16
MHz
(Operational Mode 1, 384 Fs)
(Operational Mode 2 , 192 Fs)
MCLK Duty Cycle
SCLK Frequency
(Operational
Mode 0)
12.288
-
42.24
MHz
40
-
-
-
20
20
20
20
50
-
-
-
-
-
-
-
60
%
Hz
Hz
Hz
ns
ns
ns
ns
(Operational Mode 1)
(Operational Mode 2)
256×Fs
128×Fs
64×Fs
-
-
-
-
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
t
slrd
t
slrs
t
sdlrs
t
sdh
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 1. Serial Audio Input Timing
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