參數(shù)資料
型號(hào)： CDB43122
廠商： Cirrus Logic, Inc.
英文描述： 122dB, 24-Bit, 192kHz DAC for Digital Audio
中文描述： 122分貝，24位，192kHz的數(shù)字音頻數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 523K
代理商： CDB43122
CS43122
16
MCLK
10
Master Clock
(Input) -
The master clock frequency must be either 256x, 384x,
512x or 768x the input sample rate in Operational Mode 0; either 128x, 192x 256x
or 384x the input sample rate in Operational Mode 1 ; or 64x, 96x 128x or 192x the
input sample rate in Operational Mode 2 . Tables 4-6 illustrate the standard audio
sample rates and the required master clock frequencies.
SCLK
11
Serial Clock
(Input) - Clocks individual bits of serial data into the SDATA pin. The
required relationship between the Left/Right clock, serial clock and serial data is
defined by either the Mode Control Byte in Control Port Mode or the M0 - M4 pins
in Hardware Mode. The options are detailed in Figures 20-23.
Left/Right Clock
(Input) - The Left/Right clock determines which channel is cur-
rently being input on the serial audio data input, SDATA. The frequency of the
Left/Right clock must be at the input sample rate. Audio samples in Left/Right
sample pairs will be simultaneously output from the digital-to-analog converter
whereas Right/Left pairs will exhibit a one sample period difference. The required
relationship between the Left/Right clock, serial clock and serial data is defined by
the Mode Control Byte and the options are detailed in Figures 20-23.
Serial Audio Data
(Input) - Two’s complement MSB-first serial data is input on
this pin. The data is clocked into SDATA via the serial clock and the channel is
determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte
and the options are detailed inin Figures 20-23.
LRCK
12
SDATA
13
Sample Rate
(kHz)
32
44.1
48
Table 1. Operational Mode 0 (16 to 55 kHz sample rates) Common Clock
Frequencies
MCLK (MHz)
384x
12.2880
16.9344
18.4320
256x
8.1920
11.2896
12.2880
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Sample Rate
(kHz)
48
64
88.2
96
Table 2. Operational Mode 1 (45 to 105 kHz sample rates) Common Clock
Frequencies
MCLK (MHz)
192x
8.1920
12.2880
16.9344
18.4320
128x
6.1440
8.1920
11.2896
12.2880
256x
12.2880
16.3840
22.5792
24.5760
384x
16.3840
24.5760
33.8688
36.8640
Sample Rate
(kHz)
176.4
192
Table 3. Operational Mode 2 (95 to 200 kHz sample rates) Common Clock
Frequencies
MCLK (MHz)
96x
16.9344
18.4320
64x
128x
22.5792
24.5760
192x
33.8688
36.8640
11.2896
12.2880
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