參數(shù)資料
型號: CDB42L51
廠商: Cirrus Logic, Inc.
英文描述: Silver Mica Capacitor; Capacitance:120pF; Capacitance Tolerance:+/- 5%; Series:CDV16; Voltage Rating:1000VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.94mm; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述: 低功耗,立體聲耳機放大器編解碼器
文件頁數(shù): 42/83頁
文件大?。?/td> 1348K
代理商: CDB42L51
42
DS679A2
CS42L51
4.10
Software Mode
The control port is used to access the registers allowing the CODEC to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in 2 modes: SPI and I2C, with the CODEC acting as a slave device. SPI mode is
selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high.
I2C mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.10.1
SPI Control
In SPI mode, CS is the
CS42L51
chip select signal, CCLK is the control port bit clock (input into the
CS42L51 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked
in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ig-
nored.
Figure 24
shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement
after each byte is read or written, allowing block reads or writes of successive registers.
4.10.2
I2C Control
In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected
through a resistor to VL or DGND as desired. The state of the pin is sensed while the
CS42L51
is being
reset.
The signal timings for a read and write cycle are shown in
Figure 25
and
Figure 26
. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42L51
after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write).
The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a
CS42L51
, the chip
address field, which is the first byte sent to the
CS42L51
, should match 100101 followed by the setting of
the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
4 5 6 7
CCLK
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
1 0 0 1 0 1 0 0
CDIN
INCR
6 5 4 3 2 1 0
7 6 1 0
0 1 2 3
8 9
12
16 17
10 11
13 14 15
DATA +n
CS
7 6 1 0
Figure 24. Control Port Timing in SPI Mode
相關PDF資料
PDF描述
CDB42L50 Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:No RoHS Compliant: No
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相關代理商/技術參數(shù)
參數(shù)描述
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