參數(shù)資料
型號(hào)： CDB42L51
廠商： Cirrus Logic, Inc.
英文描述： Silver Mica Capacitor; Capacitance:120pF; Capacitance Tolerance:+/- 5%; Series:CDV16; Voltage Rating:1000VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.94mm; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 低功耗，立體聲耳機(jī)放大器編解碼器
文件頁(yè)數(shù)： 40/83頁(yè)
文件大?。?/td> 1348K
代理商： CDB42L51
40
DS679A2
CS42L51
4.7
Initialization
The initialization and Power-Down sequence flow chart is shown in
Figure 23 on page 41
. The CODEC en-
ters a Power-Down state upon initial power-up. The interpolation & decimation filters, delta-sigma modula-
tors and control port registers are reset. The internal voltage reference, multi-bit DAC and ADC and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in
“Software Mode” on page 42
. If a valid write sequence to the control port is not made within approximately
10 ms, the CODEC will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, DAC_FILT+ and
ADC_FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges
the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the an-
alog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK
period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.8
Recommended Power-Up Sequence
1.
Hold RESET low until the power supplies are stable.
2.
Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3.
For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
by”.
4.
Load the desired register settings while keeping the PDN bit set to ‘1’b.
5.
Start MCLK to the appropriate frequency, as discussed in
Section 4.5
.
6.
Set the PDN bit to ‘0’b.
7.
Apply LRCK, SCLK and SDIN for normal operation to begin.
8.
Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
相關(guān)PDF資料
PDF描述
CDB42L50 Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:No RoHS Compliant: No
CDB43122 122dB, 24-Bit, 192kHz DAC for Digital Audio
CDB4327 Low Cost, 20-Bit, Stereo, Audio D/A Converter
CDB4328 18-Bit, Stereo D/A Converter for Digital Audio
CDB4329 20-Bit, Stereo D/A Converter for Digital Audio
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB42L51/FAE 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR THE CS42L51 PORTABLE STEREO CODEC - Bulk
CDB42L52 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd LP CODEC w/classD Spkr Driver RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB42L52/FAE 制造商:Cirrus Logic 功能描述:EVAL BD LOW-VOLTAGE STEREO CODEC - Bulk
CDB42L55 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd Ultra Low PWR Stereo Codec RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB42L56 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd 24Bit Ultra LP Ster CD w/clH HP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
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