參數(shù)資料
型號: CDB42L50
廠商: Cirrus Logic, Inc.
英文描述: Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:No RoHS Compliant: No
中文描述: 低電壓,立體聲耳機(jī)放大器編解碼器
文件頁數(shù): 52/83頁
文件大?。?/td> 1348K
代理商: CDB42L50
52
DS679A2
CS42L51
6.6
ADC Control (Address 06h)
ADCX High-Pass Filter Enable (ADCX_HPFEN)
Default: 1
0 - High-pass filter is disabled
1 - High-pass filter is enabled
Function:
When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter
will be disabled. For DC measurements, this bit must be cleared to ‘0’. See “ADC Digital Filter Characteris-
tics” on page 15.
ADCX High-Pass Filter Freeze (ADCX_HPFRZ)
Default: 0
0 - Continuous DC Subtraction
1 - Frozen DC Subtraction
Function:
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC
offset is frozen and this DC offset will continue to be subtracted from the conversion result. For DC mea-
surements, this bit must be set to ‘1’. See “ADC Digital Filter Characteristics” on page 15.
Soft Ramp CHX Control (SOFTX)
Def
ault: 0
0 - Disabled
1 - Enabled
Function:
Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital atten-
uation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period.
PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB
steps and be implemented on a signal zero crossing.
Zero Cross CHX Control (ZCROSSX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible
artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximate-
ly 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function
is independently monitored and implemented for each channel.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps
and be implemented on a signal zero crossing.
The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit.
7
6
5
4
3
2
1
0
ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ
SOFTB
ZCROSSB
SOFTA
ZCROSSA
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參數(shù)描述
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CDB42L52 功能描述:音頻 IC 開發(fā)工具 Eval Bd LP CODEC w/classD Spkr Driver RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB42L52/FAE 制造商:Cirrus Logic 功能描述:EVAL BD LOW-VOLTAGE STEREO CODEC - Bulk
CDB42L55 功能描述:音頻 IC 開發(fā)工具 Eval Bd Ultra Low PWR Stereo Codec RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V