參數(shù)資料
型號: CDB42L50
廠商: Cirrus Logic, Inc.
英文描述: Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:No RoHS Compliant: No
中文描述: 低電壓,立體聲耳機放大器編解碼器
文件頁數(shù): 20/83頁
文件大小: 1348K
代理商: CDB42L50
20
DS679A2
CS42L51
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Notes:
13. Response is clock dependent and will scale with Fs. Note that the response plots (
Figures 35
and
36 on
page 78
) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
14. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C
LOAD
= 15 pF.)
Parameter
(Note 13)
)
Min
-0.01
0
0
0.5465
50
-
-
-
-
Typ
-
-
-
-
-
9/Fs
-
-
-
Max
+0.08
0.4780
0.4996
-
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
Unit
dB
Fs
Fs
Fs
dB
s
dB
dB
dB
Frequency Response 10 Hz to 20 kHz
Passband
to -0.05 dB corner
to -3 dB corner
StopBand
StopBand Attenuation
(Note 14)
Group Delay
De-emphasis Error
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Parameters
Symbol
Min
Max
Units
RESET
pin Low Pulse Width
(Note 15)
1
-
ms
MCLK Frequency
1.024
38.4
MHz
MCLK Duty Cycle
(Note 16)
45
55
%
Slave Mode
Input Sample Rate (LRCK)
Quarter-Speed Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
F
s
F
s
F
s
F
s
4
8
4
50
12.5
25
50
100
kHz
kHz
kHz
kHz
LRCK Duty Cycle
45
55
%
SCLK Frequency
1/t
P
-
64F
s
55
Hz
SCLK Duty Cycle
45
%
LRCK Setup Time Before SCLK Rising Edge
t
s(LK-SK)
t
d(MSB)
t
s(SDO-SK)
t
h(SK-SDO)
t
s(SD-SK)
t
h
40
-
ns
LRCK Edge to SDOUT MSB Output Delay
-
40
ns
SDOUT Setup Time Before SCLK Rising Edge
30
-
ns
SDOUT Hold Time After SCLK Rising Edge
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
20
-
ns
SDIN Hold Time After SCLK Rising Edge
20
-
ns
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