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參數(shù)資料
| 型號(hào)： | CDB4272 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 24-Bit, 192 kHz Stereo Audio CODEC |
| 中文描述： | 24位192千赫立體聲音頻CODEC |
| 文件頁數(shù)： | 26/53頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | CDB4272 |
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CS4272
26
DS593F1
5.1.4
16-Bit Auto-Dither
The CS4272 will auto-configure to output properly dithered 16-bit data when placed in Slave Mode and a 32x SCLK
to LRCK ratio is used. In this configuration, one half of a bit of dither is added to the LSB of the 16-bit word. This
applies only to the serial audio output of the ADC and will not affect DAC performance. See Figure 9.
5.1.5
Auto-Mute
The DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sam-
ple of non-static data will release the mute. Detection and muting are done independently for each channel. The
common mode on the output will be retained and the Mute Control pin for that channel will go active during the mute
period.
5.1.6
High Pass Filter
The operational amplifiers in the input circuitry driving the CS4272 may generate a small DC offset into the ADC.
The CS4272 includes a high pass filter after the decimator to remove any DC offset which could result in recording
a DC level, possibly yielding "clicks" when switching between devices in a multichannel system.
In Stand-Alone Mode, the high pass filter continuously subtracts a measure of the DC offset from the output of the
decimation filter. This function cannot be disabled in Stand-Alone Mode.
5.1.7
Interpolation Filter
In Stand-Alone Mode, the fast roll-off interpolation filter is used.
Filter specifications can be found in Section 3. Plots of the data are contained in the “Appendix” on page 47.
5.1.8
Mode Selection & De-Emphasis
The sample rate, Fs, can be adjusted from 4 kHz to 200 kHz. In Stand-Alone Mode, the CS4272 must be set to the
proper mode via the mode pins, M1 and M0. De-emphasis, optimized for a 44.1 kHz sampling frequency, is avail-
able.
Table 5. CS4272 Stand-Alone Mode Control
5.1.9
Either I
2
S or left justified serial audio data format may be selected in Stand-Alone Mode. The selection will affect
both the input and output format. Placing a 10 k
pull-up to VL on the I2S/LJ pin will select the I
2
S format, while
placing a 10 k
pull-down to DGND on the I2S/LJ pin will select the left justified format.
Serial Audio Interface Format Selection
Mode 1
0
0
1
1
Mode 0
0
1
0
1
Mode
Sample Rate (Fs)
4 kHz - 50 kHz
4 kHz - 50 kHz
50 kHz - 100 kHz
100 kHz - 200 kHz
De-Emphasis
44.1 kHz
Off
Off
Off
Single Speed Mode
Single Speed Mode
Double Speed Mode
Quad Speed Mode
16-Bit W ord
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Dither
Figure 9. ADC 16-Bit Auto-Dither
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