參數(shù)資料
型號(hào)： CDB4270
廠商： Cirrus Logic, Inc.
元件分類(lèi)： Codec
英文描述： 24-Bit, 192 kHz Stereo Audio CODEC
中文描述： 24位192千赫立體聲音頻CODEC
文件頁(yè)數(shù)： 31/48頁(yè)
文件大?。?/td> 730K
代理商： CDB4270
DS686A1
31
CS4270
6. CONTROL PORT INTERFACE
The Control Port is used to load all the internal settings of the CS4270. The operation of the Control Port may be
completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control
Port pins should remain static if no operation is required.
The Control Port has 2 modes: SPI and I2C, with the CS4270 operating as a slave to control messages in both
modes. If I2C operation is desired, AD0/CS should be tied to VLC or DGND. If the CS4270 ever detects a high to
low transition on AD0/CS after power-up, SPI mode will be selected.
Upon release of the RST pin, the CS4270 will wait approximately 10 ms before it begins its start-up sequence. The
part defaults to Stand-Alone Mode, in which all operational modes are controlled as described in
Section 5.1 on
page 22
. If the user initiates communication to the part through the SPI or I2C interface, the part enters Control-Port
Mode and all operational modes are controlled by the Control Port registers. If system requirements do not allow
writing to the control port immediately following the release of RST, the SDIN line should be held at logic “0” until
the proper serial mode can be selected.
6.1
SPI
Mode
In SPI mode, CS is the CS4270 chip select signal, CCLK is the control port bit clock, CDIN is the input data
line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is
clocked in on the rising edge of CCLK.
Figure 16
shows the operation of the Control Port in SPI mode. To write to a register, bring CS low. The first
7 bits on CDIN form the chip address, and must be 1001111. The eighth bit is a read/write indicator (R/W),
which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the
address of the register that is to be updated. The next 8 bits are the data which will be placed into the register
designated by the MAP. See
Table 9 on page 35
.
The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the
MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte
is written, allowing block writes to successive registers.
MAP
MSB
LSB
DATA
byte 1
byte n
R/W
MAP = Memory Address Pointer
ADDRESS
1001111
CHIP
CDIN
CCLK
CS
Figure 16. Control Port Timing, SPI mode
相關(guān)PDF資料
PDF描述
CDB4271 24-Bit, 192 kHz Stereo Audio CODEC
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CDB43122 122dB, 24-Bit, 192kHz DAC for Digital Audio
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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