參數(shù)資料
型號: CDB4270
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 24-Bit, 192 kHz Stereo Audio CODEC
中文描述: 24位192千赫立體聲音頻CODEC
文件頁數(shù): 25/48頁
文件大?。?/td> 730K
代理商: CDB4270
DS686A1
25
CS4270
5.2.3 System Clocking
The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three
speed modes as shown in
Table 4
.
5.2.4 Clock Ratio Selection
In Control Port Master Mode, the user must configure the mode bits (M0, M1, M2) to set the speed mode
and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave Mode,
different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control Port Reg-
ister Bits are shown in
Table 5
,
Table 9
and
Section 8.3 on page 35
.
Mode
Sampling Frequency
4-54 kHz
50-108 kHz
100-216 kHz
Single-Speed
Double-Speed
Quad-Speed
Table 4. Speed Modes
Master Mode
SCLK/LRCK
MCLK/LRCK
LRCK
MCLK
Freq<2>
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
MCLK
Freq<1>
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
MCLK
Freq<0>
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
Single-Speed
256
384
512
768
1024
128
192
256
384
512
64
96
128
192
256
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Double-Speed
Quad-Speed
Slave Mode
SCLK/LRCK
MCLK/LRCK
LRCK
MCLK
Freq<2>
0
0
0
0
1
MCLK
Freq<1>
0
0
1
1
0
MCLK
Freq<0>
0
1
0
1
0
Single-Speed
256
384
512
768
1024
32, 64, 128
32, 48, 64, 96, 128
32, 64, 128
32, 48, 64, 96, 128
32, 64, 128
Fs
Fs
Fs
Fs
Fs
Table 5. Clock Ratios - Control Port Mode
相關(guān)PDF資料
PDF描述
CDB4271 24-Bit, 192 kHz Stereo Audio CODEC
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