參數(shù)資料
型號: CDB4270
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 24-Bit, 192 kHz Stereo Audio CODEC
中文描述: 24位192千赫立體聲音頻CODEC
文件頁數(shù): 23/48頁
文件大小: 730K
代理商: CDB4270
DS686A1
23
CS4270
5.1.4 Clock Ratio Selection
Depending on whether the CS4270 is in Master or Slave Mode, different MCKL/LRCK and SCLK/LRCK
ratios may be used. These ratios are shown in the
Table 2
.
5.1.5 Interpolation Filter
In Stand-Alone Mode, the fast roll-off interpolation filter is used. Filter specifications can be found in
Sec-
tion 3
. Plots of the data are contained in
Section 11. “Appendix” on page 42
.
5.1.6 High-Pass Filter
The operational amplifiers in the input circuitry driving the CS4270 may generate a small DC offset into
the ADC. The CS4270 includes a high-pass filter after the decimator to remove any DC offset which could
result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel
system. In Stand-Alone Mode, the high-pass filter continuously subtracts a measure of the DC offset from
the output of the decimation filter This function cannot be disabled in Stand-Alone Mode.
Master Mode
MCLK/LRCK
256
384
512
1024
128
192
256
512
64
96
128
256
SCLK/LRCK
64
64
64
64
64
64
64
64
64
64
64
64
LRCK
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
MDIV2
0
0
1
1
0
0
1
1
0
0
1
1
MDIV1
0
1
0
1
0
1
0
1
0
1
0
1
Single-Speed
Double-Speed
Quad-Speed
Slave Mode
MCLK/LRCK
256
384
512
1024
128
192
256
512
64
96
128
256
SCLK/LRCK
32, 48, 64, 128
32, 48, 64, 96
32, 48, 64, 128
32, 48, 64, 96
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
LRCK
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
MDIV2
0
0
1
1
0
0
1
1
0
0
1
1
MDIV1
0
1
0
1
0
1
0
1
0
1
0
1
Single-Speed
Double-Speed
Quad-Speed
Table 2. Clock Ratios - Stand-Alone Mode
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