參數(shù)資料
型號(hào): CDB4245
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC
中文描述: 105分貝24位192千赫Streo蘇迪奧編解碼器
文件頁數(shù): 40/54頁
文件大?。?/td> 1166K
代理商: CDB4245
CS4245
40
6.3
DAC Control - Address 03h
6.3.1
DAC Functional Mode (Bits 7:6)
Function:
Selects the required range of input sample rates.
6.3.2
DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital
Interface Format and the options are detailed in Table 6 and Figures 7-9.
6.3.3
Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this
bit is active high, it should be noted that the MUTEC pin is active low. The common mode voltage on
the outputs will be retained when this bit is set. The muting function is effected, similar to attenuation
changes, by the DACSoft and DACZero bits in the DAC Control 2 register.
6.3.4
De-Emphasis Control (Bit 1)
Function:
The standard 50/15
μ
s digital de-emphasis filter response, Figure 20, may be implemented for a sam-
ple rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 7 below. NOTE: De-em-
phasis is available only in Single-Speed Mode.
7
6
5
4
3
2
1
0
DAC_FM1
DAC_FM0
DAC_DIF1
DAC_DIF0
Reserved
MuteDAC
DeEmph
DAC_M/S
Table 5. Functional Mode Selection
DAC_FM1
0
0
1
1
DAC_FM0
0
1
0
1
Mode
Single-Speed Mode: 4 to 50 kHz sample rates
Double-Speed Mode: 50 to 100 kHz sample rates
Quad-Speed Mode: 100 to 200 kHz sample rates
Reserved
Table 6. DAC Digital Interface Formats
DAC_DIF1
0
0
1
1
DAC_DIF0
0
1
0
1
Description
Format
0
1
2
3
Figure
7
8
9
9
Left Justified, up to 24-bit data (default)
I
2
S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
Table 7. De-Emphasis Control
DeEmph
0
1
Description
Disabled (default)
44.1 kHz de-emphasis
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