參數(shù)資料
型號(hào): CDB42448
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 108 dB, 192 kHz 6-in, 8-out CODEC
中文描述: 108分貝192千赫6 - 8 -出編解碼器
文件頁數(shù): 39/70頁
文件大?。?/td> 1146K
代理商: CDB42448
DS648PP2
39
dressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is
set to 1, the data for successive registers will appear consecutively.
4.7.2
In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock,
SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip ad-
dress and should be connected through a resistor to VLC or DGND as desired. The state of the
pins is sensed while the CS42448 is being reset.
The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start con-
dition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising
transition while the clock is high. All other transitions of SDA occur while the clock is low. The
first byte sent to the CS42448 after a Start condition consists of a 7 bit chip address field and a
R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at
10010. To communicate with a CS42448, the chip address field, which is the first byte sent to
the CS42448, should match 10010 followed by the settings of the AD1 and AD0. The eighth bit
of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address
Pointer (MAP) which selects the register to be read or written. If the operation is a read, the con-
tents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an ac-
knowledge bit. The ACK bit is output from the CS42448 after each input byte is read, and is input
to the CS42448 from the microcontroller after each transmitted byte.
I
2
C Mode
Since the read operation can not set the MAP, an aborted write operation is used as a preamble.
As shown in Figure 25, the write operation is aborted after the acknowledge for the MAP byte
by sending a stop condition. The following pseudocode illustrates an aborted write operation fol-
lowed by a read operation.
Send start condition.
Send 10010xx0 (chip address & write operation).
Receive acknowledge bit.
4 5 6 7
24 25
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 0 AD1 AD0 0
SDA
INCR
6 5 4 3 2 1 0
7 6 1 0
7 6 1 0
7 6 1 0
0 1 2 3
8 9
12
16 17 18 19
10 11
13 14 15
27 28
26
DATA +n
Figure 24. Control Port Timing, I2C Write
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 0 AD1 AD0 0
SDA
1 0 0 1 0 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR
6 5 4 3 2 1 0
7 0
7 0
7 0
NO
16
8 9
12 13 14 15
4 5 6 7
0 1
20 21 22 23 24
26 27 28
2 3
10 11
17 18 19
25
ACK
DATA + n
STOP
Figure 25. Control Port Timing, I2C Read
相關(guān)PDF資料
PDF描述
CDB4245 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC
CDB42518 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
CDB42528 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
CDB4270 24-Bit, 192 kHz Stereo Audio CODEC
CDB4271 24-Bit, 192 kHz Stereo Audio CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB4245 功能描述:音頻 IC 開發(fā)工具 Eval Bd 192kHz CODEC w/PGA & Input Mux RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB42518 功能描述:音頻 IC 開發(fā)工具 Eval Bd RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB42528 功能描述:音頻 IC 開發(fā)工具 Eval Bd RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4265 功能描述:音頻 IC 開發(fā)工具 Eval Bd 192kHz CODEC w/PGA & Input Mux RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4270 功能描述:音頻 IC 開發(fā)工具 Eval Bd 105dB 192kHz CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V