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參數(shù)資料
| 型號： | CDB42438 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 108 dB, 192 kHz 4-in, 6-out TDM CODEC |
| 中文描述： | 108分貝192千赫4 - 6 -出的TDM編解碼器 |
| 文件頁數(shù)： | 31/62頁 |
| 文件大?。?/td> | 1004K |
| 代理商： | CDB42438 |
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DS673PP2
31
De-emphasis is only available in Single Speed Mode.
Please see “DAC De-Emphasis Control
(DAC_DEM)” on page 43 for de-emphasis control.
5.4
The CODEC serial audio interface ports operate as a slave and accept externally generated clocks.
The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must
be an integer multiple of, and synchronous with, the system sample rate, Fs.
Hardware Mode
The allowable ratios include 256Fs and 512Fs in Single-Speed Mode and 256Fs in Double-Speed Mode.
The frequency of MCLK must be specified using the MFREQ (pin 3). See Table 3 below for the required
frequency range.
System Clocking
Software Mode
The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency
(MFreq[2:0])” on page 42.
5.5
The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with vary-
ing bit depths from 16 to 32 as shown in Figure 13. Data is clocked out of the ADC on the falling edge of
SCLK and clocked into the DAC on the rising edge.
TDM is the only interface supported in hardware and software mode.
CODEC Digital Interface
5.5.1
Data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring
after an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is transmitted
early but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted
on the falling edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left justified
within the time slot. Valid data lengths are 16, 18, 20, or 24.
SCLK must operate at 256Fs. FS identifies the start of a new frame and is equal to the sample
rate, Fs.
TDM
Ratio (xFs)
DSM
N/A
256
MFREQ
Description
1.5360 MHz to 12.8000 MHz
2.0480 MHz to 25.6000 MHz
SSM
256
512
QSM
N/A
N/A
0
1
Table 3. MCLK Frequency Settings
Gain
dB
-10dB
0dB
Frequency
T2 = 15 μs
T1=50 μs
F1
F2
3.183 kHz
10.61 kHz
Figure 12. De-Emphasis Curve
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB42448 | 108 dB, 192 kHz 6-in, 8-out CODEC |
| CDB4245 | 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC |
| CDB42518 | 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver |
| CDB42528 | 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver |
| CDB4270 | 24-Bit, 192 kHz Stereo Audio CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4244 | 制造商:Cirrus Logic 功能描述:EVAL BD 4 INPUT/ 4 OUTPUT CODEC - Boxed Product (Development Kits) 制造商:Cirrus Logic 功能描述:Eval Board |
| CDB42448 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 108dB 8-Ch Mult-Ch CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4245 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 192kHz CODEC w/PGA & Input Mux RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB42518 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB42528 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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