參數(shù)資料
型號(hào): CDB42428
廠(chǎng)商: Cirrus Logic, Inc.
元件分類(lèi): Codec
英文描述: 114 dB, 192kHz 8-Ch CODEC WITH PLL
中文描述: 114分貝,192kHz的8通道編解碼器與鎖相環(huán)
文件頁(yè)數(shù): 27/67頁(yè)
文件大?。?/td> 1433K
代理商: CDB42428
27
CS42428
not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W)
high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave
the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will
appear consecutively.
3.6.2
In I
2
C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS42428 is being reset.
I
2
C Mode
The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42428 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42428,
the chip address field, which is the first byte sent to the CS42428, should match 10011 followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto incre-
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS42428 after each input byte is read, and is input to the
CS42428 from the microcontroller after each transmitted byte.
4 5 6 7
24 25
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 AD1 AD0 0
SDA
INCR
6 5 4 3 2 1 0
7 6 1 0
7 6 1 0
7 6 1 0
0 1 2 3
8 9
12
16 17 18 19
10 11
13 14 15
27 28
26
DATA +n
Figure 18. Control Port Timing, I
2
C Slave Mode Write
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 AD1 AD0 0
SDA
1 0 0 1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR
6 5 4 3 2 1 0
7 0
7 0
7 0
NO
16
8 9
12 13 14 15
4 5 6 7
0 1
20 21 22 23 24
26 27 28
2 3
10 11
17 18 19
25
ACK
DATA + n
STOP
Figure 19. Control Port Timing, I
2
C Slave Mode Read
相關(guān)PDF資料
PDF描述
CDB42438 108 dB, 192 kHz 4-in, 6-out TDM CODEC
CDB42448 108 dB, 192 kHz 6-in, 8-out CODEC
CDB4245 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC
CDB42518 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
CDB42528 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB42438 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd 108dB 6&8-Ch Mult-Ch CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4244 制造商:Cirrus Logic 功能描述:EVAL BD 4 INPUT/ 4 OUTPUT CODEC - Boxed Product (Development Kits) 制造商:Cirrus Logic 功能描述:Eval Board
CDB42448 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd 108dB 8-Ch Mult-Ch CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4245 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd 192kHz CODEC w/PGA & Input Mux RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
CDB42518 功能描述:音頻 IC 開(kāi)發(fā)工具 Eval Bd RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V