參數(shù)資料
型號: CDB42428
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 114 dB, 192kHz 8-Ch CODEC WITH PLL
中文描述: 114分貝,192kHz的8通道編解碼器與鎖相環(huán)
文件頁數(shù): 24/67頁
文件大小: 1433K
代理商: CDB42428
CS42428
24
3.5.4.3
OLM Config #3
This configuration will support up to 8 channels of DAC data, and 6 channels of ADC data. OLM Config
#3 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz.
Since the ADCs data stream is configured to use the ADC_SDOUT output and the internal and external
ADCs are clocked from the ADC_SP, then the sample rate for the DAC Serial Port can be different from
the sample rate of the ADC serial port.
Register / Bit Settings
Description
Functional Mode Register (addr = 03h)
Set DAC_FMx = 00,01,10
Set ADC_FMx = 00,01,10
Set ADC_CLK_SEL = 1
Interface Format Register (addr = 04h)
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01
Set DAC_OLx bits = 00,01,10
Misc. Control Register (addr = 05h)
Set DAC_SP M/S = 1
Set ADC_SP M/S = 0 or 1
Set EXT ADC SCLK = 0
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK
Configure ADC_SDOUT to be clocked from the ADC_SP clocks.
Select the digital interface format when not in one line mode
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Set DAC Serial Port to master mode.
Set ADC Serial Port to master mode or slave mode.
Identify external ADC clock source as ADC Serial Port.
DAC Mode
Not One Line Mode
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
not valid
One Line Mode #1
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
not valid
One Line Mode #2
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
not valid
ADC Mode
Not One
Line Mode
One Line
Mode #1
One Line
Mode #2
SCLK_PORT1
LRCK_PORT1
SDIN_PORT1
SCLK_PORT2
LRCK_PORT2
SDOUT1_PORT2
SDOUT2_PORT2
SDOUT3_PORT2
SDOUT4_PORT2
RMCK
ADCIN1
ADCIN2
MCLK
SDOUT1
SDOUT2
LRCK
SCLK
64Fs,128Fs
DIGITAL AUDIO
PROCESSOR
CS5361
CS5361
ADC_SCLK
ADC_LRCK
ADC_SDOUT
DAC_SCLK
DAC_LRCK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
MCLK
64Fs,128Fs,256Fs
Figure 15. OLM Configuration #3
CS42428
相關PDF資料
PDF描述
CDB42438 108 dB, 192 kHz 4-in, 6-out TDM CODEC
CDB42448 108 dB, 192 kHz 6-in, 8-out CODEC
CDB4245 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC
CDB42518 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
CDB42528 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
相關代理商/技術參數(shù)
參數(shù)描述
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