參數資料
型號： CDB42428
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： 114 dB, 192kHz 8-Ch CODEC WITH PLL
中文描述： 114分貝，192kHz的8通道編解碼器與鎖相環(huán)
文件頁數： 15/67頁
文件大?。?/td> 1433K
代理商： CDB42428
15
CS42428
sample rate applications are shown in Table 1. The lock time is the worst case for an Fs transition from un-
locked state to locking to 192 kHz.
It is important to treat the LPFLT pin as a low level analog input. It is suggested that the ground end of the
PLL filter be returned directly to the AGND pin independently of the digital ground plane.
3.4.2
OMCK System Clock Mode
A special clock switching mode is available that allows the clock that is input through the OMCK pin to
be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock
Control (address 06h)” on page 37. An advanced auto switching mode is also implemented to maintain
master clock functionality. The clock auto switching mode allows the clock input through OMCK to be
used as a clock in the system without any disruption when the PLL loses lock, for example, when the
LRCK is removed from ADC_LRCK. This clock switching is done glitch free.
3.4.3
Master Mode
In master mode, the serial interface timings are derived from an external clock attached to OMCK or the
output of the PLL with an input reference to the ADC_LRCK input from the ADC serial port. The DAC
Serial Port and ADC Serial Port can both be masters only when OMCK is used as the clock source. When
using the PLL output, the ADC Serial Port must be slave and the DAC Serial Port can operate in Master
Mode. Master clock selection and operation is configured with the SW_CTRL1:0 and CLK_SEL bits in
the Clock Control Register (See “Clock Control (address 06h)” on page 37).
The sample rate to OMCK ratios and OMCK frequency requirements for Master mode operation are
shown in Table 2.
3.4.4
Slave Mode
In Slave mode, DAC_LRCK, DAC_SCLK and/or ADC_LRCK and ADC_SCLK operate as inputs. The
Left/Right clock signal must be equal to the sample rate, Fs and must be synchronously derived from the
supplied master clock, OMCK or must be synchronous to the supplied ADC_LRCK used as the input to
Fs Range (kHz) RFILT (k
) CFILT (pF) CRIP (pF)
32 to 192
10
Settling time
11 ms
2700
680
Table 1. PLL External Component Values
Sample
Rate
(kHz)
OMCK (MHz)
Double Speed
(50 to 100 kHz)
128x
192x
-
12.2880 18.4320 24.5760
-
-
Single Speed
(4 to 50 kHz)
256x
12.2880
18.4320 24.5760
-
-
-
-
Quad Speed
(100 to 192 kHz)
64x
96x
-
-
12.2880 18.4320 24.5760
384x
512x
256x
-
128x
-
-
48
96
192
-
-
-
-
-
-
Table 2. Common OMCK Clock Frequencies
相關PDF資料
PDF描述
CDB42438 108 dB, 192 kHz 4-in, 6-out TDM CODEC
CDB42448 108 dB, 192 kHz 6-in, 8-out CODEC
CDB4245 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC
CDB42518 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
CDB42528 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
相關代理商/技術參數
參數描述
CDB42438 功能描述:音頻 IC 開發(fā)工具 Eval Bd 108dB 6&8-Ch Mult-Ch CODEC RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4244 制造商:Cirrus Logic 功能描述:EVAL BD 4 INPUT/ 4 OUTPUT CODEC - Boxed Product (Development Kits) 制造商:Cirrus Logic 功能描述:Eval Board
CDB42448 功能描述:音頻 IC 開發(fā)工具 Eval Bd 108dB 8-Ch Mult-Ch CODEC RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4245 功能描述:音頻 IC 開發(fā)工具 Eval Bd 192kHz CODEC w/PGA & Input Mux RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB42518 功能描述:音頻 IC 開發(fā)工具 Eval Bd RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
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