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參數(shù)資料
| 型號(hào)： | CDB42418 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 110 dB, 192kHz 8-Ch CODEC WITH PLL |
| 中文描述： | 110分貝，192kHz的8通道編解碼器與鎖相環(huán) |
| 文件頁數(shù)： | 14/67頁 |
| 文件大?。?/td> | 1433K |
| 代理商： | CDB42418 |
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CS42418
14
3.4
The clock generation for the CS42418
is shown in the figure below. The internal MCLK is derived from
the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of
PLL lock to the other source input.
Clock Generation
3.4.1
PLL and Jitter Attenuation
The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and
generate the required internal master clock frequency. There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to
have good jitter attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register “Clock
Control (address 06h)” on page 37, the PLL will lock to the incoming ADC_LRCK and generate an output
master clock (RMCK) of 256Fs. Table 3 below shows the output of the PLL with typical input Fs values
for ADC_LRCK.
The PLL behavior is affected by the external filter component values. Figure 1 shows the required config-
uration of the external filter components. The set of component values required for 32 kHz to 192 kHz
ADC_LRCK
(slave mode)
PLL (256Fs)
8.192 -
49.152 MHz
00
01
PLL_LRCK bit
SW_CTRLx bits
(manual or auto
switch)
OMCK
Auto Detect
Input Clock
1,1.5, 2, 4
single
speed
256
double
speed
128
quad
speed
64
single
speed
4
double
speed
2
quad
speed
1
00
01
10
00
01
10
00
01
10
00
01
10
not OLM
OLM #1
DAC_FMx bits
ADC_FMx bits
DAC_OLx
or ADC_OLx bits
ADC_OLx and
ADC_SP SELx bits
ADC_SCLK
DAC_SCLK
DAC_LRCK
ADC_LRCK
RMCK
OLM #2
not OLM
OLM #1
OLM #2
128FS
256FS
128FS
256FS
Internal
MCLK
00
01
10
11
RMCK_DIVx bits
2
4
X2
Figure 6. Clock Generation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB42426 | 114 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42428 | 114 dB, 192kHz 8-Ch CODEC WITH PLL |
| CDB42438 | 108 dB, 192 kHz 4-in, 6-out TDM CODEC |
| CDB42448 | 108 dB, 192 kHz 6-in, 8-out CODEC |
| CDB4245 | 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB42426 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42428 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd CBD42418/28 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB42438 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 108dB 6&8-Ch Mult-Ch CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4244 | 制造商:Cirrus Logic 功能描述:EVAL BD 4 INPUT/ 4 OUTPUT CODEC - Boxed Product (Development Kits) 制造商:Cirrus Logic 功能描述:Eval Board |
| CDB42448 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 108dB 8-Ch Mult-Ch CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
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