參數(shù)資料
型號： CDB4228A
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： 24-Bit, 96 kHz Surround Sound Codec
中文描述： 24位96千赫環(huán)繞聲解碼器
文件頁數(shù)： 27/32頁
文件大小： 518K
代理商： CDB4228A
CS4228A
DS511PP1
27
LRCK
6
Left/Right Clock
(Bidirectional) - The Left/Right clock determines which channel is cur-
rently being input or output on the serial audio data output, SDOUT. The frequency of the
Left/Right clock must be at the output sample rate, Fs. In Master mode, LRCK is an output,
in Slave Mode, LRCK is an input whose frequency must be equal to Fs and synchronous to
the Master clock.
Audio samples in Left/Right pairs represent simultaneously sampled analog inputs whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship
between the Left/Right clock, serial clock and serial data is defined by the Serial Port Mode
register. The options are detailed in Figures 9, 10, 11 and 12
.
Digital Ground
(Input) - Digital Ground Reference.
Digital Power
(Input) - Digital Power Supply. Typically 5.0 VDC.
Digital Interface Power
(Input) - Digital interface power supply. Typically 2.5, 3.3 or
5.0 VDC. All digital output voltages and input threshholds scale with VL.
Master Clock
(Input) - The master clock frequency must be either 128x, 256x, 384x or
512x the input sample rate in Base Rate Mode (BRM) and either 64x, 128x, 192x, or 256x
the input sample rate in High Rate Mode (HRM). Table 2 illustrates several standard audio
sample rates and the required master clock frequencies. The MCLK/Fs ratio is set by the
CI1:0 bits in the CODEC Clock Mode register.
Sample
Rate
(kHz)
64x
128x
192x
256x
32
-
-
-
-
44.1
-
-
-
-
48
-
-
-
-
64
4.0960
8.1920
12.2880 16.3840
88.2
5.6448
11.2896
16.9344 22.5792
96
6.1440
12.2880
18.4320 24.5760
Table 2. Common Master Clock Frequencies
DGND
VD
VL
7
8
9
MCLK
10
SCL/CCLK
11
Serial Control Interface Clock (
Input) - Clocks the serial control data into or out of
SDA/CDIN.
Serial Control Data I/O
(Bidirectional/Input) - In two wire mode, SDA is a bidirectional con-
trol port data line. A pull up resistor must be provided for proper open drain output operation.
In SPI mode, CDIN is the control port data input line. The state of the SDOUT pin during
reset is used to set the control port mode.
Address Bit 0 / Chip Select
(Input) - In two wire mode, AD0 is the LSB of the chip
address. In SPI mode, CS is used as a enable for the control port interface.
Reset
(Input) -
When low, the device enters a low power mode and all internal registers
are reset to the default settings, including the control port. The control port can not be
accessed when reset is low.
When high, the control port and the CODEC become operational.
Mute Control
(Output) - The Mute Control pin goes low during the following conditions: pow-
er-up initialization, power-down, reset, no master clock present, or if the master clock to
left/right clock frequency ratio is incorrect. The Mute Control pin can also be user controlled
by the MUTEC bit in the DAC Mute2 Control register. Mute Control can be automatically as-
serted when 512 consecutive zeros are detected on all six DAC inputs, and automatically
deasserted when a single non-zero value is sent to any of the six DACs. The mute on zero
function is control
led by the MUTCZ bit in the DAC Mute2 Control register. The MUTEC pin
is intended to be used as a control for an external mute circuit to achieve a very low noise
floor during periods when no audio is present on the DAC outputs, and to prevent the clicks
and pops that can occur in any single supply system. Use of the Mute Control pin is not man-
da
tory but recommended.
SDA/CDIN
12
ADO/CS
13
RST
14
MUTEC
15
MCLK (MHz)
HRM
BRM
128x
4.0960
5.6448
6.1440
-
-
-
256x
8.1920
11.2896 16.9344 22.5792
12.2880 18.4320 24.5760
-
-
-
-
-
-
384x
12.2880 16.3840
512x
-
-
-
相關(guān)PDF資料
PDF描述
CDB4228 24-Bit, 96 kHz Surround Sound Codec
CDB42416 110 dB, 192kHz 6-Ch CODEC WITH PLL
CDB42418 110 dB, 192kHz 8-Ch CODEC WITH PLL
CDB42426 114 dB, 192kHz 6-Ch CODEC WITH PLL
CDB42428 114 dB, 192kHz 8-Ch CODEC WITH PLL
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CDB42416 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:110 dB, 192kHz 6-Ch CODEC WITH PLL
CDB42418 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:110 dB, 192kHz 8-Ch CODEC WITH PLL
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