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參數(shù)資料
| 型號： | CDB4228A |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 24-Bit, 96 kHz Surround Sound Codec |
| 中文描述： | 24位96千赫環(huán)繞聲解碼器 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 518K |
| 代理商： | CDB4228A |
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CS4228A
26
DS511PP1
6. PIN DESCRIPTION
SDIN1, SDIN2,
SDIN3
1, 2, 3
Serial Audio Data In
(Input) - Two’s complement MSB-first serial audio data is input on this
pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is
determined by the Left/Right clock. The required relationship between the Left/Right clock,
serial clock and serial data is defined by the Serial Mode Register. The options are detailed
in Figures 9, 10, 11, and 12.
Serial Audio Data Out
(Output) - Two’s complement MSB-first serial data is output on this
pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by
the Left/Right clock. The required relationship between the Left/Right clock, serial clock and
serial data is defined by the Serial Mode Register. The options are detailed in Figures 9, 10,
11 and 12.
The state of the SDOUT pin during reset is used to set the Control Port Mode (two wire or
SPI). When RST is low, SDOUT is configured as an input, and the rising edge of RST
latches the state of the pin. A weak internal pull up is present such that a resistive load less
than 47 k
will pull the pin low, and the control port mode is two wire. When the resistive
load on SDOUT is greater than 47 k
during reset, the control port mode is SPI.
Serial Clock
(Bidirectional) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins,
and out of the SDOUT pin. The pin is an output in master mode, and an input in slave
mode.
In master mode, SCLK is configured as an output. MCLK is divided internally to generate
SCLK at the desired multiple of the sample rate.
In slave mode, SCLK is configured as an input. The serial clock can be provided externally,
or the pin can be grounded and the serial clock derived internally from MCLK.
The required relationship between the Left/Right clock, serial clock and serial audio data is
defined by the Serial Port Mode register. The options are detailed in Figures 9, 10, 11, and
12.
SDOUT
4
SCLK
5
Serial Audio Data In 3
Serial Audio Data In 2
Serial Audio Data In 1
Serial Audio Data Out
Serial Clock
Left/Right Clock
Digital Ground
Digital Power
Digital Interface Power
Master Clock
SDIN3
SDIN2
SDIN1
SDOUT
SCLK
LRCK
DGND
SUB
CENTER
Analog Out #5, Center
SR
Analog Out #4, Surround Right
SL
Analog Out #3, Surround Left
FR
Analog Out #2, Front Right
FL
Analog Out #1, Front Left
AGND
Analog Ground
VA
Analog Power
AINL+
Left Channel Analog Input+
AINL-
Left Channel Analog Input-
FILT
Internal Voltage Filter
AINR
-
Right Channel Analog Input-
AINR
+
Right Channel Analog Input+
MUTEC
Mute Control
Analog Out #6,Subwoofer
VD
VL
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
Reset
SCL/CCLK
SDA/CDIN
AD0/CS
RST
3
4
7
8
9
10
11
12
13
5
6
1
2
24
23
22
21
20
19
18
17
16
15
14
25
26
27
28
相關PDF資料 |
PDF描述 |
|---|---|
| CDB4228 | 24-Bit, 96 kHz Surround Sound Codec |
| CDB42416 | 110 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42418 | 110 dB, 192kHz 8-Ch CODEC WITH PLL |
| CDB42426 | 114 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42428 | 114 dB, 192kHz 8-Ch CODEC WITH PLL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDB42324 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 2-In 4-Out Mult. -Ch CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB42325 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:10-In, 6-Out, 2 Vrms Audio CODEC with Headphone |
| CDB42406 | 制造商:Cirrus Logic 功能描述:EVAL BD FOR CS42406 - Bulk |
| CDB42416 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:110 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42418 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:110 dB, 192kHz 8-Ch CODEC WITH PLL |
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