參數(shù)資料
型號: CDB4228A
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 24-Bit, 96 kHz Surround Sound Codec
中文描述: 24位96千赫環(huán)繞聲解碼器
文件頁數(shù): 25/32頁
文件大?。?/td> 518K
代理商: CDB4228A
CS4228A
DS511PP1
25
5.9 Serial Port Mode
Address 0x0D
DCK1:0
Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)
DMS1:0
Sets the master/slave mode of the serial audio port
*0 -
Slave (External LRCLK, SCLK)
1 -
Reserved
2 -
Reserved
3 -
Master (No 48 Fs SCLK in BRM
DDF2:0
Serial Port Data Format
0 -
Right Justified, 24-bit
1 -
Right Justified, 20-bit
2 -
Right Justified, 16-bit
3 -
Left Justified, maximum 24-bit
*4 -
I
2
S compatible, maximum 24-bit
5 -
One-line Data Mode, available in BRM only
6 -
Reserved
7 -
Reserved
5.10 Chip Status
Address 0x0E
CLKERR
Clocking system status, read only
0 -
No Error
1 -
No MCLK is present, or a request for clock change is in progress
ADCOVL
ADC overflow bit, read only
0 -
No overflow
1 -
ADC overflow has occurred
7
6
5
4
3
2
1
0
DCK1
1
DCK0
0
DMS1
0
DMS0
0
RESERVED
0
DDF2
1
DDF1
0
DFF0
0
DCK1:0
0
1
2
3
BRM (Fs)
32 (1)
48 (2)
*64
128
HRM (Fs)
(3)
(3)
32 (1)
64
Notes: 1.
All formats will default to 16 bits
External Slave mode only
Invalid mode
2.
3.
7
6
5
4
3
2
1
0
CLKERR
X
ADCOVL
X
RESERVED
0
0
0
0
0
0
相關(guān)PDF資料
PDF描述
CDB4228 24-Bit, 96 kHz Surround Sound Codec
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CDB42418 110 dB, 192kHz 8-Ch CODEC WITH PLL
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CDB42428 114 dB, 192kHz 8-Ch CODEC WITH PLL
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