- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379828 > CDB4228A (Cirrus Logic, Inc.) 24-Bit, 96 kHz Surround Sound Codec PDF資料下載
參數(shù)資料
| 型號： | CDB4228A |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 24-Bit, 96 kHz Surround Sound Codec |
| 中文描述： | 24位96千赫環(huán)繞聲解碼器 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 518K |
| 代理商： | CDB4228A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
CS4228A
18
DS511PP1
Since the read operation can not set the MAP, an
aborted write operation is used as a preamble. As
shown in Figure 15, the write operation is aborted
after the acknowledge for the MAP byte by sending
a stop condition. The following pseudocode illus-
trates an aborted write operation followed by a read
operation.
Send start condition.
Send 001000x0 chip address & write operation.
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 001000x1 chip address & read operation.
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows
successive reads or writes of consecutive registers.
Each byte is separated by an acknowledge bit.
3.8 Control Port Bit Definitions
All registers are read/write, except the Chip Status
register which is read-only. For more detailed in-
formation, see the bit definition tables.
3.9 Power-up/Reset/Power Down Mode
Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers are reset to their default
settings, and the device remains in a low power
mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in re-
set, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.
4 5 6 7
24 25
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
0 0 1 0 0 AD1 AD0 0
SDA
INCR
6 5 4 3 2 1 0
7 6 1 0
7 6 1 0
7 6 1 0
0 1 2 3
8 9
12
16 17 18 19
10 11
13 14 15
27 28
26
DATA +n
Figure 14. Control Port Timing, Two Wire Slave Mode Write
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
0 0 1 0 0 AD1 AD0 0
SDA
0 0 1 0 0 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR
6 5 4 3 2 1 0
7 0
7 0
7 0
NO
16
8 9
12 13 14 15
4 5 6 7
0 1
20 21 22
23 24
26 27 28
2 3
10 11
17 18 19
25
ACK
DATA + n
STOP
Figure 15. Control Port Timing, Two Wire Slave Mode Read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB4228 | 24-Bit, 96 kHz Surround Sound Codec |
| CDB42416 | 110 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42418 | 110 dB, 192kHz 8-Ch CODEC WITH PLL |
| CDB42426 | 114 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42428 | 114 dB, 192kHz 8-Ch CODEC WITH PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB42324 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 2-In 4-Out Mult. -Ch CODEC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB42325 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:10-In, 6-Out, 2 Vrms Audio CODEC with Headphone |
| CDB42406 | 制造商:Cirrus Logic 功能描述:EVAL BD FOR CS42406 - Bulk |
| CDB42416 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:110 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42418 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:110 dB, 192kHz 8-Ch CODEC WITH PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復。