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參數(shù)資料
| 型號： | CDB4228A |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 24-Bit, 96 kHz Surround Sound Codec |
| 中文描述： | 24位96千赫環(huán)繞聲解碼器 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大小： | 518K |
| 代理商： | CDB4228A |
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CS4228A
DS511PP1
17
3.7 Control Port Signals
Internal registers are accessed through the control
port. The control port may be operated asynchro-
nously with respect to audio sample rate. However,
to avoid potential interference problems, the con-
trol port pins should remain static if no register ac-
cess is required.
The control port has 2 operating modes: SPI mode
and two wire mode. In both modes the CS4228A
operates as a slave device. Mode selection is deter-
mined by the state of the SDOUT pin when RST
transitions from low to high: high for SPI, low for
two wire mode. SDOUT is internally pulled high to
VL. A resistive load from SDOUT to GND of less
than 47 k
will enable two wire mode after a hard-
ware reset.
3.7.1 SPI Mode
In SPI mode, CS is the CS4228A chip select signal,
CCLK is the control port bit clock input, and CDIN
is the input data line. There is no data output line,
therefore all registers are write-only in SPI mode.
Data is clocked in on the rising edge of CCLK.
Figure 13 shows the operation of the control port in
SPI mode. The first 7 bits on CDIN, after CS goes
low, form the chip address (0010000). The eighth
bit is a read/write indicator (R/W), which should al-
ways be low to write. The next 8 bits set the Mem-
ory Address Pointer (MAP) which is the address of
the register that is to be written. The following
bytes contain the data which will be placed into the
registers designated by the MAP.
The CS4228A has a MAP auto increment capabili-
ty, enabled by the INCR bit in the MAP register. If
INCR is zero, then the MAP will stay constant for
successive writes. If INCR is 1, then the MAP will
increment after each byte is written, allowing block
reads or writes of successive registers.
3.7.2 Two Wire Mode
In two wire mode, SDA is a bidirectional data line.
Data is clocked into and out of the port by the SCL
clock. The signal timing is shown in Figures 14
and 15. A Start condition is defined as a falling
transition of SDA while the clock is high. A Stop
condition is a rising transition while the clock is
high. All other transitions of SDA occur while the
clock is low.
The first byte sent to the CS4228A after a Start con-
dition consists of a 7 bit chip address field and a
R/W bit (high for a read, low for a write). The AD0
pin determines the LSB of the chip address field.
The upper 6 bits of the address field must be 00100
and the seventh bit must match AD0. If the opera-
tion is to be a write, the second byte is the Memory
Address Ponter (MAP), which selects the register
to be written. The succeeding byte(s) are data. If
the operation is to be a read, the second byte is sent
from the chip to the controller and contains the con-
tents of the register pointed to by the current value
of the MAP.
CS
CCLK
(input)
12 13 14 15
CDIN
(input)
CHIP ADDRESS (WRITE)
MAP BYTE
0 0 1 0 0 0 0 0
MSB
DATA
DATA +n
R/W
INCR
8 9 10 11
4 5 6 7
0 1 2 3
16 17 18 19 20 21 22
23
(input)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Figure 13. Control Port Timing, SPI Slave Mode Write
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PDF描述 |
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| CDB4228 | 24-Bit, 96 kHz Surround Sound Codec |
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| CDB42418 | 110 dB, 192kHz 8-Ch CODEC WITH PLL |
| CDB42426 | 114 dB, 192kHz 6-Ch CODEC WITH PLL |
| CDB42428 | 114 dB, 192kHz 8-Ch CODEC WITH PLL |
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