參數(shù)資料
型號(hào): CDB4228
廠商: Cirrus Logic, Inc.
元件分類(lèi): Codec
英文描述: 24-Bit, 96 kHz Surround Sound Codec
中文描述: 24位96千赫環(huán)繞聲解碼器
文件頁(yè)數(shù): 6/30頁(yè)
文件大?。?/td> 487K
代理商: CDB4228
CS4228
6
DS307PP1
ANALOG CHARACTERISTICS
(Continued)
DIGITAL CHARACTERISTICS
Unless otherwise specified (T
A
= 25 °C; VD = VL = +3.3V;
VA =+ 5V)
SWITCHING CHARACTERISTICS
(T
A
= 25°C; VD = VL = +3.3V, VA = +5V, outputs loaded with
30 pF)
Power Supply
Power Supply Current
VA = 5V, VD = VL = 3.3V
Symbol
Min
Typ
Max
Min
Typ
Max
Units
Operating
VA
VL
VD
Power Down
VA
VL
VD
-
-
-
-
-
-
-
25
2
42
TBD
2
0.1
50
TBD
TBD
TBD
TBD
TBD
TBD
-
-
-
-
-
-
-
25
2
48
TBD
2
0.1
50
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
dB
Power Supply Rejection
(1 kHz, 10 mV
rms
)
Parameter
Symbol
V
IH
V
IL
V
OH
V
OL
Min
0.7xVL
Typ
-
-
-
-
-
-
Max
-
0.3xVL
-
0.4
10
10
Units
V
V
V
V
μ
A
μ
A
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage at I
0
= -2.0 mA
Low-level Output Voltage at I
0
= 2.0 mA
Input Leakage Current
Output Leakage Current
VL - 1.0
-
-
-
(Digital Inputs)
(High-Impedance Digital Outputs)
Parameter
Symbol
Fs
Min
30
60
3.84
Typ
-
-
-
Max
50
100
25.6
Units
kHz
kHz
MHz
Audio ADC's & DAC's Sample Rate
BRM
HRM
MCLK Frequency
MCLK Duty Cycle
BRM
MCLK =128, 384 Fs
MCLK = 256, 512 Fs
HRM
MCLK = 64, 192 Fs
MCLK = 128, 256 Fs
TBD
40
TBD
40
-
50
50
-
500
TBD
60
TBD
60
-
%
%
%
%
ps
MCLK Jitter Tolerance
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