參數(shù)資料
型號: CDB4228
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 24-Bit, 96 kHz Surround Sound Codec
中文描述: 24位96千赫環(huán)繞聲解碼器
文件頁數(shù): 24/30頁
文件大?。?/td> 487K
代理商: CDB4228
CS4228
24
DS307PP1
PIN DESCRIPTION
Serial Audio Data In - SDIN3, SDIN2, SDIN1
Pin 1, 2, 3, Input
Function:
Two’s complement MSB-first serial audio data is input on this pin. The data is clocked into SDIN1, SDIN2,
SDIN3 via the serial clock and the channel is determined by the Left/Right clock. The required relationship
between the Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The op-
tions are detailed in Figures 9, 10, 11 and 12.
Serial Audio Data Out - SDOUT
Pin 4, Output
Function:
Two’s complement MSB-first serial data is output on this pin. The data is clocked out of SDOUT via the
serial clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Serial Mode Register. The options are de-
tailed in Figures 9, 10, 11 and 12.
The state of the SDOUT pin during reset is used to set the Control Port Mode (I2C or SPI). When RST is
low, SDOUT is configured as an input, and the rising edge of RST latches the state of the pin. A weak
internal pull up is present such that a resistive load less than 47 k
will pull the pin low, and the control
port mode is I2C. When the resistive load on SDOUT is greater than 47 k
during reset, the control port
mode is SPI.
Serial Audio Data In 3
Serial Audio Data In 2
Serial Audio Data In 1
Serial Audio Data Out
Serial Clock
Left/Right Clock
Digital Ground
Digital Power
Digital Interface Power
Master Clock
SDIN3
SDIN2
SDIN1
SDOUT
SCLK
LRCK
DGND
AOUT6
AOUT5
AOUT4
AOUT3
AOUT2
AOUT1
AGND
VA
AINL+
AINL-
FILT
AINR
-
AINR
+
MUTEC
Analog Output 6
Analog Output 5
Analog Output 4
Analog Output 3
Analog Output 2
Analog Output 1
Analog Ground
Analog Power
Left Channel Analog Input+
Left Channel Analog Input-
Internal Voltage Filter
Right Channel Analog Input-
Right Channel Analog Input+
Mute Control
VD
VL
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
Reset
SCL/CCLK
SDA/CDIN
AD0/CS
RST
3
4
7
8
9
10
11
12
13
5
6
1
2
24
23
22
21
20
19
18
17
16
15
14
25
26
27
28
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