參數(shù)資料
型號: CDB4228
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 24-Bit, 96 kHz Surround Sound Codec
中文描述: 24位96千赫環(huán)繞聲解碼器
文件頁數(shù): 21/30頁
文件大小: 487K
代理商: CDB4228
CS4228
DS307PP1
21
DAC Mute1 Control
Address 0x04
MUT6 - MUT1
Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally
attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenu-
tation value returns to the value stored in the corresponding Digital Volume Control register. The
attenuation value is ramped up and down at the rate specified by RMP1:0.
0 -
Normal output level
*1 -
Selected DAC output fully attenuated.
RMP1:0
Attenuation ramp rate.
*0 -
0.5dB change per 4 LRCKs
1 -
0.5dB change per 8 LRCKs
2 -
0.5dB change per 16 LRCKs
3 -
0.5dB change per 32 LRCKs
DAC Mute2 Control
Address 0x05
MUTEC
Controls the MUTEC pin
*0 -
Normal operation
1 -
MUTEC pin asserted low
MUTCZ
Automatically asserts the MUTEC pin on consecutive zeros. When enabled, 512 consecutive
zeros on all six DAC inputs will cause the MUTEC pin to be asserted low. A single non-zero
value on any DAC input will cause the MUTEC pin to deassert.
*0 -
Disabled
1 -
Enabled
HMUTE56/34/12
Hard mute the corresponding DAC pair. When asserted, zero data is sent to the corresponding
DAC pair causing an instantaneous mute. To prevent high frequency transients on the outputs,
a DAC pair should be fully attenuated by asserting the corresponding MUT6-MUT1 bits in the
DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control reg-
isters before asserting HMUTE.
*0 -
Normal operation
1 -
DAC pair is muted
7
6
5
4
3
2
1
0
MUT6
1
MUT5
1
MUT4
1
MUT3
1
MUT2
1
MUT1
1
RMP1
0
RMP0
0
7
6
5
4
3
2
1
0
MUTEC
0
MUTCZ
0
RESERVED
HMUTE56
0
HMUTE34
0
HMUTE12
0
RESERVED
0
0
0
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