參數(shù)資料
型號： CDB4226
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： Surround Sound Codec
中文描述： 環(huán)繞聲編解碼器
文件頁數(shù)： 7/60頁
文件大?。?/td> 1619K
代理商： CDB4226
CS4226
DS188F1
7
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25°C; VD+, VA+ = 5V ±5%;
Inputs: logic 0 = DGND, logic 1 = VD+, C
L
= 30 pF)
Parameter
I
2
C
Mode
(SPI/I
2
C = 1)
(Note 12)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 13)
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Notes: 12.
I
2
C is a registered trademark of Philips Semiconductors.
Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
13.
S/PDIF RECEIVER CHARACTERISTICS
(RX1, RX2, RX3, RX4 pins only; VD+, VA+ = 5V ±5%)
Notes: 14.
CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384×Fs and 512×Fs as selected output frequency.
For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section.
15.
Symbol
Min
Max
Units
f
scl
t
buf
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
r
t
f
t
susp
-
100
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
Parameter
Symbol
Z
N
V
TH
V
HYST
F
S
Min
-
200
-
30
-
40
Typ
10
-
50
-
200
50
Max
-
-
-
50
-
60
Units
k
mVpp
mV
kHz
ps RMS
%
Input Resistance
Input Voltage
Input Hysteresis
Input Sample Frequency
CLKOUT Jitter
CLKOUT Duty Cycle (high time/cycle time)
(Note 14)
(Note 15)
t
buf
thdst
t
hdst
t
low
t
r
t
f
t
hdd
thigh
t
sud
t
sust
t
susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
相關(guān)PDF資料
PDF描述
CDB4228A 24-Bit, 96 kHz Surround Sound Codec
CDB4228 24-Bit, 96 kHz Surround Sound Codec
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CDB42426 114 dB, 192kHz 6-Ch CODEC WITH PLL
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