參數(shù)資料
型號: CDB4226
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: Surround Sound Codec
中文描述: 環(huán)繞聲編解碼器
文件頁數(shù): 5/60頁
文件大小: 1619K
代理商: CDB4226
CS4226
DS188F1
5
SWITCHING CHARACTERISTICS
(T
A
= 25°C; VA+, VD+ = +5V ±5%, outputs loaded with 30 pF)
Parameter
Audio ADC's & DAC's Sample Rate
XTI Frequency
(XTI = 256, 384, or 512 Fs)
XTI Pulse Width High
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI Pulse Width Low
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
PLL Clock Recovery Frequency
RX, XTI, LRCK, LRCKAUX
XTI Jitter Tolerance
PDN Low Time
(Note 9)
SCLK Falling Edge to SDOUT Output Valid
(DSCK = 0)
Notes: 9.
After powering up the CS4226, PDN should be held low until the power supply is settled.
Symbol
Fs
Min
4
1.024
10
21
31
10
21
31
30
-
500
-
Typ
-
-
-
-
-
-
-
-
-
500
-
-
Max
50
26
-
-
-
-
-
-
50
-
-
384
)
Fs
Units
kHz
MHz
ns
ns
ns
ns
ns
ns
kHz
ps
ns
ns
t
dpd
LRCK edge to MSB valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
SCLK Period
t
lrpd
t
ds
t
dh
-
-
-
-
-
-
40
25
25
ns
ns
ns
(DSCK=0)
(DSCK=0)
t
sck
-
-
ns
SCLK Falling to LRCK Edge
SCLK Duty Cycle
Slave Mode
SCLK Period
(DSCK=0)
t
mslr
-
-
±10
50
-
-
ns
%
t
sckw
-
-
ns
SCLK High Time
SCLK Low Time
SCLK Rising to LRCK Edge
LRCK Edge to SCLK Rising
t
sckh
t
sckl
t
lrckd
t
lrcks
40
40
20
40
-
-
-
-
-
-
-
-
ns
ns
ns
ns
(DSCK=0)
(DSCK=0)
(
-------1
20
+
256
(
)
Fs
-------1
128
(
)
Fs
-------1
t
mslr
SCLK*
SCLKAUX*
(output)
LRCK
LRCKAUX
(output)
SDOUT1
SDOUT2
t
sck
Audio Ports Master Mode Timing
sckh
sckl
sckw
t
t
t
MSB
MSB-1
*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0.
SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.
Audio Ports Slave Mode and Data I/O timing
t
dpd
SDOUT1
SDOUT2
LRCKAUX
(input)
LRCK
SCLK*
SCLKAUX*
(input)
SDIN1
SDIN2
SDIN3
DATAUX
dh
t
ds
t
lrpd
t
lrcks
t
lrckd
t
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